The input of ADC12D1800 in DESCLKIQ mode

Hi Guojie

The ADC12D1X00RF products do support a mode with DES (Dual Edge Sampling) and independent I and Q differential inputs. This is what we call DESCLKIQ.

In all of the other DES modes (DES-I, DES-Q, DES-IQ) the analog input signal is internally connected and routed to both I and Q converters. This helps ensure matching of amplitude and delay between the signal arriving at the I and Q converters. The DESCLKIQ mode does not have this internal connection of the signal to both converters. In this mode, the signals are completely independent, similar to the non-DES mode. Due to this difference, and the reduced loading on the signal, the bandwidth does improve. The trade-off is that the matching between I and Q signals is no longer as good. Our testing to date has found that it is nearly impossible to connect the signals externally in such a way that they will be adequately matched over input frequency. The result is that significant interleave spurs are present in the spectrum due to the amplitude and timing mismatch between the 2 input signals. In certain applications that are insensitive to these spurs, this will not be a problem. In other applications it will be necessary to add digital post-processing to correct for the mismatch and help minimize the interleaving spurs.

If your application is sensitive to interleaving spurs and you do not want to add post processing to correct for them, I would highly recommend you use the DESIQ mode instead. The bandwidth is slightly lower, but the matching between I and Q signals is much better.

I hope this is helpful.

Best regards,

Jim B

Jim, Thanks for the response.

So, the ADC12D1800RF chip is working as two independent ADCs  with the same source but phase-inversed  sampling clock in DESCLKIQ mode, right?

The ENOB, SFDR, and THD will decrease significantly due to the mismatch errors?  

Is there any testing data of these parameters(ENOB or SFDR) in DESCLKIQ mode?

If we use a power splitter (like RPS-2-30) to generate two input signals, could the perfomance of the chip (SFDR or ENOB) be improved in DESCLKIQ mode? 

Coulde I use the DES timing Ajust feature of the chip to adjust the mismatch phase that get the decreased interleaving spurs?

Hello,

I wanted to jump on this question as I have a very similar question. I am looking to use one of TIs dual ADCs in an interleaving application. The link above was useful, but I was curious as to why the datasheet states for the "Interleaved (DES) mode" the FPBW is lower. Is there a means of using a dual ADC in an interleaving application that can overcome that lower FPBW limitation? It seems that may be the case in the pdf link above, but was wondering if you could clarify? Thanks.

Hi Michael

The challenge with designing an ADC to support both 2-input (non-interleaved) and single input (interleaved) operation is that the flexibility itself generates compromises. The mux-steering circuitry must provide good channel to channel isolation (low crosstalk) in the 2-input mode. In the 1-input interleaved mode, the circuitry must deliver perfectly matched copies of the input signal to both internal converters.

The implementation in the ADC1XD1XXX(RF) Dual/Interleavable devices from TI provides very good bandwidth, channel to channel isolation and dynamic performance in 2-input mode.

In 1-input (interleaved) mode there are several options (please refer to the simplified DES mode sketches on pages 7 and 8 of the previously referenced document) :

• DESI and DESQ modes will give the best SFDR performance, but the combination of a single 100 ohm input pair and the necessary mux switches and matched routing give a lower input bandwidth than the 2-input mode.
• In DESIQ mode, both pairs of inputs must be driven with identical signals. In this configuration, two 100 ohm inputs are connected to the internal switches and routing. This gives an improvement in bandwidth, but a slight degradation in SFDR performance due to the slight degradation in interleaved signal matching.
• DESCLKIQ mode is similar to DESIQ mode, but with less internal circuitry connected to each 100 ohm input. This lower loading improves the bandwidth even further. However, since the internal I and Q signal paths are now highly isolated the matching of the signals arriving at the internal interleaved converters is significantly worse. In this mode SFDR performance is further degraded. This mode is only really recommended for applications where SRDR performance is not important.

I hope this is helpful.

Best regards,

Jim B

Jim,

Thanks for the information. From what I am reading here it sounds like our application would benefit from Option 2 the DESIQ mode as we need the input BW, but may be able to take the slight hit in SFDR for that capability. Option 1 giving the lower BW I think didn't meet our needs, and Option 3 may be too much degradation in performance to consider.

Mike

Hi Jim,

We bought a DEG FMC board with ADC-D1800RF to digitize a chirp from 1.1 to 1.8 GHz with 2 GHz sampling frequency.

If I understand well the DESCLKIQ mode could be the good mode with splitter to divide by 2 the signal in input. But I need to add processing in FPGA to perform à good synchronisation between the 2 Inputs.

Another question : what´s happen if I use overclocking method in non DES mode with sampling frequency at 2 GHz.

Thanks. You for your help...