ADS4229 sampling frequency

Joel Brenner

Other Parts Discussed in Thread: ADS4229

Hi, I'm planning to use the ADS4229 dual adc for an FPGA driven RF signal acquisition application. I need to sample 2 analog signals with a 250 MHz sampling clock.

It is not clear to me if the 250 MSPS of the ADS4229 is referring to the per channel sampling speed or the overall (2 channel ) sampling speed.

Any input ?

Thanks, Joel

over 14 years ago

0 KW Nam over 14 years ago

TI__Expert 8895 points

Hi,

ADS4229 has maximum 250Msps of sampling for each of channel. Please let me know if you have other questions.

Thanks,

0 FF over 12 years ago in reply to KW Nam

Prodigy 245 points

Hello,

how about 25MHz in CMOS mode? datasheet doesnt have any timing data for more than 200MHz CMOS!

thanks

0 LeonardEllis over 12 years ago in reply to FF

TI__Guru 71526 points

Hi Faraz,

You asked "25MHz" but I'm thinking you mean 250MHz, yes?

-L

0 KW Nam over 12 years ago in reply to LeonardEllis

TI__Expert 8895 points

From my bench test, the max speed in CMOS mode was 125MHz which is a half of LVDS speed. I'll double check this with designer of this device.

Thanks,

0 FF over 12 years ago in reply to KW Nam

Prodigy 245 points

Hi Leonard , Yes I mean 250Mhz thanks for the correction,

thanks KW for testing it,

Faraz

Data converters

Data converters forum

ADS4229 sampling frequency