ADC SPI Communication

Other Parts Discussed in Thread: TLV2543, MSP430G2553

Hello Everyone,

I have been trying to solve communication problem for more than 1 week. Still I couldn't find a solution to communicate with them. I am using MSP430g2553 microcontroller and TLV2543 ADC from TI. I have set the communication init s on MSP430 however when I send 0x14 from microcontroller which means "select second channel of ADC and give me 8 bit uni polar data." However, EOC(End of Conversion) signal coming from ADC goes from high to low when transmission just started from microcontroller to ADC, instead of some microseconds after I transmit data from microcontroller to ADC. In the following links, you can find SPI clock  vs. EOC signals, and SPI clock vs. TX data, and SPI clokc vs. ~CS. 

Here is my code, I would be really appreciate if you give me any help or suggestion.

http://imageupload.org/en/file/207682/clk-tx.jpg.html

http://www.imageupload.org/en/file/207685/clk-eoc.jpg.html

Thank you,

Deniz Akkaya

//
//                     MSP430G2553
//                  -----------------
//                 /|\|              XIN|-
//                 | |                    |
//                    --|RST  XOUT|-
//                      |                    |
//                     |            P1.2|-> Data Out (UCA0SIMO)
//                 |                    |
//                      |            P1.1|<- Data In (UCA0SOMI)
//                     |                    |
//  Slave reset <-|P1.5         P1.4|-> Serial Clock Out (UCA0CLK)
//

//******************************************************************************
#include "msp430g2553.h"

unsigned char MST_Data, SLV_Data;

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer
  
  UCA0CTL1 |= UCSWRST;                     // **Initialize USCI state machine**
  
  P1SEL =  BIT2 + BIT4 ;
  P1SEL2 =  BIT2 + BIT4;
  	
  UCA0CTL0 |= UCMSB + UCMST + UCSYNC;  	// 3-pin, 8-bit SPI master
  UCA0CTL1 |=  UCSSEL_2;        		// Clocking on Pos edge of CLK,              // SMCLK
  UCA0BR0 |= 0x02	;                          // /2
  UCA0BR1 |= 0x00	;
  UCA0MCTL = 0;                             // No modulation
  
  P1DIR |= BIT1 + BIT5;                   	  //
  
  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  
  IE2 |= UCA0RXIE;                          // Enable USCI0 RX interrupt

MST_Data = 0x14;
P1OUT |= BIT5; //reset up

__bis_SR_register(GIE);       // enable interrupts
	

while(1)
{
	
	
P1OUT &= ~BIT5;//reset down
	  _delay_cycles(2);							// wait couple of U sec for sending data; according to datasheet 	  
	  UCA0TXBUF = MST_Data;						// send data from master to slave
	  while ((UCA0STAT & UCBUSY));              // USCI_A0 TX buffer ready?
	  _delay_cycles(3);							// wait for data send complete according to datasheet
P1OUT |= BIT5;//reset up
	  IFG2 &= ~UCA0TXIFG;						// clear TX check bit						
	_delay_cycles(1000);						// wait a lot for next transmission
	  
	  	  
}

while(1);   
}


// Test for valid RX and TX character
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCIA0RX_ISR(void)
{
  	IFG2 &= ~UCA0RXIFG;							// clear reset flag when interrupt comes
  
}