Other Parts Discussed in Thread: ADS1247
Hi, I have a ADS1247 that I want to synchronize with other like devices every second.
The datasheet is not very clear with regards to what the latency of the device is after initiating an SPI SYNC command. Here is a cut and paste from page 34 of the datasheet:
The filter is reset two system clocks after the last bit
of the SYNC command is sent. The reset pulse
created internally lasts for two multiplier clock cycles.
If any write operation takes place in the MUX0
register, the filter is reset regardless of whether the
value changed or not. Internally, the filter pulse lasts
for two system clock periods. If any write activity
takes place in the VBIAS, MUX1, or SYS0 registers,
the filter is reset as well, regardless of whether the
value changed or not. The reset pulse lasts for 32
modulator clocks after the write operation. If there are
multiple write operations, the resulting reset pulse
may be viewed as the ANDed result of the different
active low pulses created individually by each action.
Here's how I understand it: 1) SYNC command -->2) wait 2 clks-->3) filter reset (2 Clks)-->4) filter pulse (2Clks)-->5) Write Activity (if any)-->6) filter reset (32 modulator clocks)-->7) filter reset wait time (approx 1 sample time)
Is my flow correct? Basically I want to understand how many clock cycles we get delayed when using the SYNC command (when in constant conversion mode)
What is a multiplier clock cycle? I can't find anything in the datasheet that defines this.
Can you clarify the last sentence? It is unclear to me.
