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ads5463, ads5400

lefteris fysikopoulos
Intellectual 320 points

Other Parts Discussed in Thread: ADS5400, ADS5463

Hello,

I would like to ask i f i would be able to clock data correctly inside a Spartan 6 FPGA at 500Msps sampling rate for ADS5463 and 1Gsps for ADS5400?

Is there any possibility that the IO frequencies of Spartan 6 might limit the maximum sample rate of these ADCs?

I would like to use these ADCs along with the Spartan 6 LX150T Development Board.

Thanks in advance,

Lefteris

  • 0
    TI__Mastermind 29220 points

    Hi,

    No one can completely answer that question until you have a design that will close timing using the design tools for that FPGA.

    But the Xilinx website reports a maximum data rate per differential IO pair of over 1000Mbps.  That is twice the data rate of the LVDS pairs coming out of the ADS5463 and also twice the data rate of the data from the ADS5400 if the ADS5400 is set up to use dual-bus mode.   The max LVDS DDR data rate into an input DDR cell in an FPGA presumes a certain amount of setup and hold time from the ADC into the FPGA, and the achievable max data rate will be less if the timing from the ADC provides a smaller total valid data window than the FPGA requires for max data rate.  And there are slower speed grade FPGAs available also, and the max advertised rate would probably be for the fastest speed grade.  But I would be very surprised if 500Mbps from the ADS5463 or ADS5400 presented a problem for the Spartan 6. 

    The Spartan 6 provides an input DDR cell and an input delay element that can be used to delay either clock or data to meet setup and hold time into the IDDR cell.  You would need to use the ADS5463 datasheet to describe a timing constraint for your design that accurately describes the timing of the LVDS data and DDR clock at the pins of the FPGA, and then the Xilinx ISE static timing analysis tools will report the margin (slack) of the timing for a given tap setting of the IDELAY.  Please see the following sketch of how we used the IDELAY and IDDR cells in a Virtex4.  Something very similar to this could be implemented in the Spartan 6 and the static timing analysis tools will tell you if you meet timing at speed.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 320 points

    Richard,

    Unfortunately, this technique cannot be used with Spartan 6 LX150T Development Platform because in order to use the BUFIO2 components to clock the entire bank you cannot use the IDELAY2 component to delay the DDR clk.

    Lefteris

  • 0 in reply to lefteris fysikopoulos
    TI__Mastermind 29220 points

    Hi,

    I am not so familiar with the details of the Spartan family and the different clock buffer types, but the IDELAY elements are put there to be used on each available differential input pair. 

    if you are using a data format that has clock-centered timing such as the ADS5400, I have found that the delay needs to be used on the data lines and not the clock signal, so if the IDELAY element is still available on the data lines then this technique would still be an option.  On a device with source-synchronous timing, you *may* need to use delay on the clock signal, and if this is not possible given the clock input pair used then you may need to use a DCM (pll or dll based digital clock manager) to delay the DDR clock by 90 degrees to meet timing into the IDDR cells.

    Regards,

    Richard P.