• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 46 subscribers
  • Views 294 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

dac5682z, how to make the dual output sync?

Huailong Qi
Prodigy 200 points
Other Parts Discussed in Thread: DAC5682Z

hi,all

as the topic ,  we get the dual DAC output of the dac5682z. and we don't know how to make them sync.I should configure which register? the config10 or the offsetA & offsetB ? now the phase deviation is about 90.

 

thank you.

  • 0
    TI__Genius 17370 points

    Huailong,

    The DAC outputs are inherently synced on the same chip. If you're seeing 90 degrees of phase difference than you are likely sending a complex signal (I and Q) to the DAC, which would be 90 degrees out of phase.

    Also, make sure to follow the recommended startup sequence listed in the datasheet.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Prodigy 200 points

    Matt Guibord,

     Thank you. Is that mean the phase difference of the dual DAC on the same chip can't be changed?

    Just beginning, the difference of the phase is very small. We try to change the registers again and again to make the dual output absolutely same, but we failed and the difference came to about 90 degrees. The input data to the DACa and DACb is also same.

  • 0 in reply to Huailong Qi
    TI__Genius 17370 points

    Huailong,

    At the beginning when the phase difference was small, what was the phase difference?

    Did you enable any of the CMIX modes? What is the frequency content that you're seeing on the output?

    Lastly, what are you using to source data to the DAC (TSW3100, TSW1400)? What is the signal that you're sending to the DAC?

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Prodigy 200 points

    Matt,

          I'm sorry that I have been busy in other things recently result in I didn't reply you in time.

    we use the 200MHz input to the clkin/clkinc, also the 200MHz clock to the DCLKP/DCLKN.

          WE found the delay between the dual channel is about 2.5ns in the oscilloscope.

    we didn't enable the cmix mode. we use the FPGA to send the sine signal to the DAC.

    regards

    huailong

  • 0 in reply to Huailong Qi
    TI__Genius 17370 points

    Huailong,

    2.5 ns is a lot of delay. Is it possible that you're clocking in samples one cycle apart? For instance your samples arrive at the DAC as A1, B0, A2, B1, A3, B2 where samples A1 and B0 are output at the same time, and A2 and B1 at the same time, and A3 and B2 at the same time. Such that they are one sample clock off? This would account for 5 ns of delay between the samples.

    Also, are you observing the outputs by connecting SMA cables from the EVM to the scope? Or are you using voltage probes at the outputs?

    In the case of SMA cables, make sure they are the same length and the same model. If you're using probes, verify that they are the same model and that the time skew has been calibrated out of them by placing them on the same exact point (channel A output?) and using the scope settings to change the skew so they match.

    Regards,
    Matt Guibord