• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 45 subscribers
  • Views 166 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE7225 DAC_DCLKIN and FIFO

jon pry
Intellectual 370 points
Other Parts Discussed in Thread: AFE7225

I'm having some trouble with the AFE7225 in LVDS mode. Currently I have CLKINN/P hooked up to DAC_FCLKN/P which is running at 100 mhz. DAC_DCLKN/P is running at 300 mhz and data is clocked in 600 mbps. All the clock dividers are set to 1 in the configuration. After applying sync internally. All the FIFO error conditions soon register.

I found the following in slos711a interesting: 

" The read pointer increments at the DAC_DCLKIN rate whereas the write pointer increments at the divided DAC_CLK rate."

This statement is worrisome. If it is true in LVDS mode then the FIFO can't work. Am I supposed to be turning on FIFO bypass or is that statement incorrect?

Thanks,

Jon Pry



  • 0
    Intellectual 370 points

    It turns out that if REG_PDN_TX is set that the TX fifo will overflow. Powering up TX before issuing sync has solved the fifo problem. Still I think the documentation is very sketchy about this and various other things. Lots of typos and bad information in the datasheet.