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Problematic ADS1298 signals (DRDY, SLCK, CS)

Ekrem Bayraktar
Expert 1190 points
Other Parts Discussed in Thread: ADS1298

Hi all,

I added below signals and request your help to solve this issue. My signals look synchronizied with each other but the signals are not clean enough, I set triggering and it seems the pulse width of DRDY and CS signals are also changing. I am using ADS1298 development board with EVM 5515.

My SCLK signal seems not clean, I read meaningless data on DOUT. I use internal clock of ADS1298 by setting CLK_SEL, therefore ADS clock is 2.048 MHz. Conversion rate is 2 KSPS. SCLK is set to 500 kHz at first to ensure two byte opcodes (WREG and RREG) will be executed properly (wait 8 clock cycles between bytes). For the SPI data operation SCLK is 4 MHZ. For 2KSPS, minimum SCLK should be 2K * 9 * 24 = 432 kHz, well below 4 MHz (I also tried lower SCLKs close to 500 kHz).

START signal is controlled with GPIO4 of 5515, RESET is controlled by GPIO1 of 5515 and both are proper. I set RESET high and give a RESET pulse and take it back to high and can observe all these signals.

GPIO_write(hGpio,CSL_GPIO_PIN1,setVal);         //RESET is high

wait(1000);  

 

GPIO_write(hGpio,CSL_GPIO_PIN1,resetVal);       //RESET is low

wait(1000);                                                          //RESET pulse

 

GPIO_write(hGpio,CSL_GPIO_PIN1,setVal);         //RESET is high again

wait(74000);

wait(74000);

 

GPIO_write(hGpio,CSL_GPIO_PIN4,resetVal);       //START is off before initializing SPI and ADS1298

wait(10);

wait(74000);         //end of START reset, now initialize SPI and set configuration...

 

GPIO_write(hGpio,CSL_GPIO_PIN4,setVal);         //START conversion

wait(100000);

I am sorry that I only have two scopes to show signals. I will try to find a multiple digital channel scope by Monday and will add extra more captures showing all signals together.

I can give all other necessary information if you ask me to.

Contributions will be appreciated.

Regards.

SCLK with CS signal #1:

SCLK with CS signal #2:

SCLK with DRDY signal #1:

SCLK with DRDY signal #2:

SCLK with DRDY signal #3:

  • TI__Guru**** 181021 points

    Hi Ekrem,

    Not sure what to tell you about your START signal to the ADS1298, perhaps you can post your code for review.  The SCLK looks almost like you are driving into a large capacitive load - if you can post some sort of schematic showing the connections between the EVM's that might help.  The changing DRDY signal may be caused by latency in your ISR.

  • in reply to Tom Hendrick
    Expert 1190 points

    Tom Hendrick said:

    Hi Ekrem,

    Not sure what to tell you about your START signal to the ADS1298, perhaps you can post your code for review. 

    It is my bad, there is not problem in START signal.

    Tom Hendrick said:

    The SCLK looks almost like you are driving into a large capacitive load - if you can post some sort of schematic showing the connections between the EVM's that might help.  The changing DRDY signal may be caused by latency in your ISR.

    I have just mounted ADS1298 daughter board onto EVM 5515, below is the pin configuration and jumper picture.

    ADS1298

    J13 Pin#

    EVM 5515

    START/CS

    1

    ADS_GPIO4

    CLKSEL

    2

    GPIO11

    CLK

    3

    SPI_CLK

    GND

    4

    GND

    NC

    5

    GPIO6 / I2S1_CLK

    GPIO1

    6

    ADS_GPIO10

    CS

    7

    SPI_CS0

    RESETB

    8

    ADS_GPIO1

    NC

    9

    GPIO7 / I2S1_FS

    GND

    10

    GND

    DIN

    11

    SPI_DX

    GPIO2

    12

    ADS_GPIO0

    DOUT

    13

    SPI_RX

    NC/START

    14

    GPIO9 / I2S1_RX 2

    DRDYB

    15

    INT1

    SCL

    16

    I2C_SCL

    NC

    17

    XF

    GND

    18

    GND

    NC

    19

    GPIO8 / I2S1_DX

    SDA

    20

    I2C_SDA

     

    21

    ADS_GPIO3

     

    22

    ADS_GPIO2
  • in reply to Tom Hendrick
    Expert 1190 points

    Tom Hendrick said:

    Hi Ekrem,

    The changing DRDY signal may be caused by latency in your ISR.

    I do not know about ISR latency could you please explain what you mean or guide me to a document.
  • in reply to Ekrem Bayraktar
    TI__Guru**** 181021 points

    Hi Ekrem,

    The DRDY output from the ADS1298 goes to INT1 on the 5515EVM.  I suspect there is an Interrupt Service Routine (ISR) in your code somewhere that starts the transfer of data from the ADS1298 to the DSP by starting up the SCLK.  When conversion results are available, the DRDY signal goes low which should trigger an interrupt and start the SCLK.  Once the ADS1298 sees the SCLK, the DRDY signal is returned high.  The time it takes (i.e. the latency) for the DSP to respond to the DRDY input can vary slightly depending on what the processor is doing when the interrupt request comes in.  The other thing here is your SCLK - you need to figure out what is causing the erratic behavior - if the ADS1298 does not see a clean clock, you can get errors in the SPI transmission.

  • in reply to Tom Hendrick
    Expert 1190 points

    Hi Tom,

    Sorry for the late reply I was trying to try your recommendations. You are right there was a problem about ISR timings, after putting some timer interrupts the problem is solved. I also realized that SCLK problem was due to one of my connectors, I also change it and signals are good except CS signal. DRDY vs. SCLK signals are below:

    As expected DRDY goes high at the first falling edge of SCLK. I couldn't be able to put a CS signal since the signal never settles although I try several trigger options. It seems always changing and pulse width of it is always changing. I read a recommendation about SPI communication that when SPI communication corrupts we can correct it by just pulling CS high and low again. But how can we toggle CS signal when CS of ADS1298 is connected to CS0 of C5515?

    I think after solving this CS problem I finally be able to read a meaningful data.

    I still need of your help.

    Regards.

  • in reply to Ekrem Bayraktar
    TI__Guru**** 181021 points

    Hi Ekrem,

    Instead of trying to use a GPIO for the /CS, have you considered using the Frame Sync signal?  You can also try simply taking the /CS input to GROUND.

  • in reply to Tom Hendrick
    Expert 1190 points

    Hi Tom,

    I do not use GPIO signal for CS, instead SPI_CS is directly connected to ADS1298 CS. I do not know about Frame Sync signal, would you please explain it? Taking CS directly to ground may solve the problem that I will try tomorrow. I will share the result here.

    Again I appreciate your help.

    Regards.

  • in reply to Ekrem Bayraktar
    Expert 1190 points

    Hi Tom,

    Here are my Signals on logic analyzer, I do not understand behavior of CS. I tried your recommendation and take CS to ground but after that DOUT signal disappeared and show always 0. START and RESET signals are also proper. Do you mean as Frame Sync the CS signal of C5515 or another signal?

    Regards.

  • in reply to Ekrem Bayraktar
    Prodigy 205 points

    hi,

    i am interfacing ADS1298 with freescale controller. my DRDY is not correct.

    could u please share  spi polarity and phase settings.

    regards,

    shreedhara