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DAC5688 loop bandwidth

Alex Wong CS
Intellectual 340 points
Other Parts Discussed in Thread: DAC5688, DAC3484
Dear All,
 
In my design, DAC5688 is used and we would like to optimize the PLL LPF.
 
After reading the "Choosing Loop BW for PLLs" presentation, it suggests a starting point where the open loop VCO phase noise intercepts the open loop PLL phase noise. A 20% margin is added to accommodate the non-ideal response of the filter. However, there is no such plot in the DAC5668 datasheet.
 
Right now, we use the DAC5688 LPF excel calculator, and we choose loop BW = 500KHz.
This is just a mid value in between the recommended range 100KHz to 1MHz.
 
Any advise on this matter such that I can get a more optimized loop filter values?
Thank you for your advice.
 
Regards,
Alex
  • 0
    TI__Guru* 78844 points

    Alex,

     

    I would say this is a good start. This is within the recommended guidelines that we have.

     

    Typically, the phase noise of the PLL is primarily determined by the PFD frequency and the total divided ratio at the output. In theory, the higher the PFD frequency, the faster the loop updates and yields better phase noise. You can adjust the PFD based on your reference frequency using M and N divider.

     

    Also, in theory, the phase noise will improve by 6dB for every divide-by-two operation. This includes the FVCO/2 divider and the equivalent divide-ratio of the output frequency when compared to the DAC sample clock (i.e Fout/Fdac). If your DAC sampling rate is less than 455MHz, then you may use the FVCO/2 mode to get the extra /2 operation. Of course, there is a limit due to the inherent noise of the DAC itself.

     

    To get the best phase noise, I would use the highest PFD frequency and the highest divider ratio possible, and then design a loop filter that have good phase margin.

     -KH

  • 0 in reply to Kang Hsia
    Intellectual 340 points

    KH,

    Thank you for your reply.

    I got a set of RC values based on Fdac = Fvco = 400MHz, M = 4 and N = 1. The intended Fref is 100MHz.

    This is designed in our board but have not test them yet.

    About FVCO/2 mode, I do not get the "equivalent divide-ratio of the output frequency when compared to the DAC sample clock (i.e Fout/Fdac)", isn't it the DAC output is sampled based on the Fdac? Please kindly explain.

    Also, will I get better performance and noise by using FVCO = 800MHz and the FVCO/2 mode? In this case, both Fdac and Fref remain as above, just M = 8.

    I can do some rework to try this out later, so your advice is appreciated.

    Regards,

    Alex

  • 0 in reply to Alex Wong CS
    TI__Guru* 78844 points

    Alex,

    Theoretically, whenever you have a divide-by-2 operation, you should expect a 6dB improvement of phase noise when compared to the original clock. The same concept is applied to the FVCO/2 mode. When the VCO clock is divided by two before going to the DAC, the phase noise of the DAC sample clock improves by 6dB in theory. By increasing your multiplier ratio by 2x and then applies FVCO/2, the final DAC sample rate remains at 400MHz.

    To take advantage of this principle, some of our new generation DACs with integrated VCO such as the DAC3484 family has higher VCO range (3.3GHz to 4GHz range) so we can take advantage of the prescaler to help improve the phase noise of DAC sample clock. 

    The same concept also applies to the DAC output. Assuming the DAC is just outputting a single tone, the phase noise difference of different output frequencies can be predicted by 20*log(FDAC/FOUT). For instance, you will see 6dB better performance when comparing 50MHz with 100MHz output. Basically, the DAC is doing divider function. This principle is useful if you are using the DAC to generate the tones with best phase noise (i.e. direct digital synthesis (DDS) applications). 

    -KH