Other Parts Discussed in Thread: ADS5463-SP, ADS5463, DAC5675
Hi,
We are interfacing the digital output side of a ADS5463-SP directly to Xilinx Virtex-5 LVDS receivers. Our plan is to also clock the ADS5463-SP at a ~150MHz rate from an output structure of the Xilinx. My question is regarding the FPGA ==> ADS5463-SP clock interface. I would prefer to use differential clock signalling from the Xilinx to the ADC, but making a direct differential connection doesn't seem feasible given the Xilinx output capabilities. I noticed that in the ADS5463-SP datasheet (SGLS378B), on page 17, there is a discussion about using an AC-coupled single-ended clock input. That discussion indicates that; "In low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock (see Figure 18) could save some cost and board space without any trade-off in performance." Can you define "low-input-frequency"?
