TSW1200 EVM

Hi,

The TSW1200 has a hard limit of 250MHz for the memory buffers in the FPGA.  You will see on the TSW1200 there is a small surface mount 4-pin 200MHz crystal oscillator.  The 200MHz is used by Xilinx to calibrate the IDELAY cells used to meet timing into the FPGA, and we generate an internal 250MHz from this.  We use all the available internal memory in the FPGA for bufefr storage, and the fastest that this large memory could run was 250MHz in a synchronous mode.  As a truly asynchronous FIFO of this large size it would be even slower.  So we have a very small FIFO that is a truly asynchronous FIFO that catches the data from the ADC, and then using the 250HMz internal system clock we move the sample data from the small FIFO to the large buffer memory.   Once the data rate from the ADC goes even a little over 250Msps, the small FIFO will fill fastert than the 250MHz can unload it, and when the small FIFO overflows then data samples are lost - corrupting your capture and the FFT.

I've tried editing the FPGA firmware to generate a faster internal system clock than 250MHz, but the large buffer memories begin to fail long before 400MHz. 

The way we handle data from a device such as ADS5463 at 500Msps is that the LVDS data bus is sample-wise DDR so after the data is latched into the FPGA by the IDDR cells we get two data paths at 250MHz each.  So we store 2 samples at a time at 250MHz, staying under the 250MHz limit.  Likewise for the ADS5400 at 1000Msps we run the ADC in dual bus mode with each bus in byte-wise DDR mode, letting us store 4 samples at a time at 250MHz.

For devices that are bit-wise DDR such as ADS4149, we have to take both odd and even data streams off the IDDR cells and interleave them back to a full sample, giving us a hard limit of 250Msps for storing data.

It would be messy and hard to debug maybe, but you could set up the TSW1200 to store the data from the ADC as if it were byte-wise DDR such that all the resing edge bits of the sample were stored in memory at 200Msps and at the same time all the falling edge bits of the sample were stored in memory at 200Msps.  Then after you unload the data using the Matlab interface, you could reassemble the odd and even bits back together into a sample in software and *then* process with the FFT routine.  You would need to edit the Matlab to set up the TSW1200 to store the samples as if they were byte-wise and the register space in the FPGA is not publicly documented in such a way as to make this editing easy for you.  That is why we set up the Matlab interfaces for different EVM types,  so that you would not need to know how to set register bits for different TI devices.  You are trying to do something outside of that original intent.  But you could get the Matlab interface for a device such as ADS5463 or ADS5474 and look to see how that Matlab code sets up the FPGA register space differently and between the two sets of Matlab interfaces cobble together one that does just what you need.  Again, it sounds like a bit of a messy task to make this work.

Regards,

Richard P.