SPI configuration For ADS1298

Hi Tarun,

What is the frequency of your external modulator clock source to the ADS1298?  After you set PWDN and RESET to 1, what do you see on the DRDY pin? 

Hi Tarun,

You need to wait at least 8 clk cycles for two bytes opcodes (RREG and WREG) as written in ADS1298 data sheet. Therefore you need to slow down your SPI CLK.

Regards.

Dear Tom,

Frequency of external oscillator is 2.048 MHZ, and SPI frequency is 300KHz. I am getting constantly High .

Dear Ekrem,

My SPI speed is 300Khz.

Hi Tarun,

Let's start with the DRDY.  If all the power rails are correctly applied to the ADS1298 and if you have RESET=PWDN=1, CLKSEL = 0, CLK = 2.048MHz from an external source with START = 1, you should see the DRDY pulse go high 250 times/second.  Have a look at Figure 41 in the data sheet.  If you don't see DRDY, please go back and verify all the connections on your board. 

Once you see DRDY, you can start looking into your code.  Power up the ADS1298, send the SDATAC command followed by RREG and look for the device ID bits and other default register states.  From there, try setting different registers with values other than their defaults and see if you can read them back.