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Regarding Buffer Model Selection For Virtex 6 FPGA

Ashutosh Kumar
Prodigy 20 points

Other Parts Discussed in Thread: ADC08D1520

Hi All,

I have ADC(from Texas Instrument) interfaced with FPGA(virtex 6 SX315T) and want to do SI Analysis. The model selector which are available are as follows:

[Model Selector]  lvds_hs
lvds_lo_vbgf      output voltage=lo, vbg=floating
lvds_hi_vbgf      output voltage=hi, vbg=floating
lvds_lo_vbg1      output voltage=lo, vbg=hi
lvds_hi_vbg1      output voltage=hi, vbg=hi

Please let me know which buffer model I need to select out of the above 4 model selector to do simulation for LVDS

Regards,

Ashutosh Kumar

  • 0
    TI__Mastermind 44680 points

    Hi Ashutosh

    I am assuming your question relates to the ADC08D1520 device. If you are refering to a different ADC, please let us know the particular part number.

    The model choice depends on the following conditions:

    lvds_lo_vbgf      output voltage=lo, vbg=floating
    lvds_hi_vbgf      output voltage=hi, vbg=floating
    lvds_lo_vbg1      output voltage=lo, vbg=hi
    lvds_hi_vbg1      output voltage=hi, vbg=hi

    The output voltage (LVDS output Vod control) selection is controlled by the state of the OutV logic input pin (If ADC is on non-ECM mode) or the OV register bit (Register Addr 1h, Bit 9).

    The common mode voltage of the LVDS outputs is controlled by the state of the Vbg pin. If this pin is floating the common mode is at the default level. If Vbg is tied to Va (1.9V supply) then the output common mode is at the higher setting.

    Best regards,

    Jim B