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ADS5271 Serial interface configuration

Pablo Moreno
Prodigy 40 points
Other Parts Discussed in Thread: ADS5271, ADS5270

Hello, 

I am currently working in a project to interface TI ADS5271 ADCs from a Xilinx Virtex 5 FPGA. For the moment I am implementing the functionality for configuring the ADC internal registers.

From the device datasheet I extract that I have to perform a reset pulse, wait for the stablished time, then I enable CS signal, and after that I am ready to perform the serial transfer of the configuration data using SDATA and SCLK.

I generate these signals from the FPGA, using a state machine (as well as RESET and CS). My problem is that im not sure if I have to write all the ADC internal registers, or only those that Im interested in. In addition, assuming that I have to write all the registers of the ADC, Im not sure if I have to assert and deassert the CS signal for every single register write operation, or if I have to assert it, write all the registers in a row, and then deassert it. In the device datasheet the waveforms for this operation are not clear enough for me. 

I did some tests configuring the ADC to provide the SYNC or DESKEW pattern, disabling some channel outputs in order to check I was doing the configuration of all registers correctly, but the behavior I see on the waveforms is not what I expect.

Any comment or suggestion on that?

Thanks very much in advanced.

  • 0
    TI__Mastermind 29220 points

    Hi,

    You do not need to write to all the registers.  If you do a reset, then the registers are all set to their default values and then you can change only the registers you wish to change.  Be careful of registers that have more than one function set in them - such as register 0001 that can set the LVDS current for the clock adn the lsb/msb first mode.  If you write to that register to set the bit for msb-first then you are also writing to the bits for the other function even if you did not wish to change that function away from default.  If you want to keep the default config for those bits then you need to write the default config for those bits when you write to other bits in that register.

    I like to test my SPI write ability by setting a bit for something very obvious, such as power-down - and then watch to see that the current draw for the device really did change significantly lower.

    Be careful of whether the rising edge or falling edge of the SCLK is used to latch in the data bit.  We like to make the state machine use three cycles for every bit of the data to be written such that the clock follows the pattern LOW-HIGH-LOW during the time that the data bit is set.  This way the data is valid around both the rising and falling adges of the SCLK and there can be no mistake as to whether we used the right edge of the SCLK.  It does not matter if the SCLK has a resulting duty cycle that is not 50/50.

    I believe you would need to bring SEN back high after each register write.  We have some newer devices that will allow you to pack several register writes into a single cycle of SEN being low, but the data sheet in that case makes it clear when that is allowed.   Other devices will take only as many bits as is needed to fill one address and one data field for a register access adn discard any extra bits during that cycle of SEN being low.  In this case, shift in only 8 bits during each cycle of SEN being low for the four address and four data bits.  Use another cycle of SEN for the next register write.

    For example, to set the device for the SYNC test pattern, bring SEN low and hold it low.  Then for 8 cycles of SCLK being low then high, make the data pattern be 0, 0, 0, 0, 1, 0, 0, 0 to shift in address 0000 and the data value 1000.  Then bring SEN back high.

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 40 points

    Hi Richard,

    Thanks a lot for your fast response. I was doing everything right except the issue of enabling and disabling CS (SEN) in every transferred word. That explains that the only register I was able to write was R0 ( I was able to see the SYNC pattern but not the effect of other registers, like disabling certain channels, for example). 

    What about the SCLK frequency? It is recommended to have a SCLK period of at least 50 ns. I was using 100 ns (since there is no upper bound). What do you recommend regarding frequencies and waveform times, like t_reset or t_cs? I was thinking in making  them last 1'5 times the minimum recommended by the documentation.

    Pablo.

  • 0 in reply to Pablo Moreno
    TI__Mastermind 29220 points

    Hi,

    You should be able to trust the minimum values listed in the datasheet, but if you want to design for 1.5 times those values to give some margin on your side, then that is fine.  That way if there is some tolerance on your system clock that generates these signals, for example, then you would know you are still in a safe region.  For the SCLK period, there is not a max value, really, as you can make the interface about as slow as you wish.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 40 points

    Hello again, 

    I have been doing some configuration tests with the ADS5271. It seems that I am able to write correctly many internal registers. In parituclar I have been able to write:

    R0: I have put the ADC on normal operation mode, deskew pattern, sync pattern and custom pattern

    R1: I have put the ADC on both MSB and LSB modes

    R4, R5, R6: I have succesfuly introduced my custom pattern into the ADC

    The only problem I have is with the power-down of individual channels. I try to write on R2 and R3, but I don´t see the effect on the waveforms. I expect the selected channel outputs to be fixed in a logical 0. Am I rigth?

    I don't understand what  I am doing wrong, since the write operation is the same as in the rest of registers, I only change the value of the adress and data to be transferred.

    In our board, the PD pin is set to GND (normal mode). Does it have something to do?

    Thanks very much.

    Best regards.

  • 0 in reply to Pablo Moreno
    TI__Mastermind 29220 points

    Hi,

    I have an ADS5270 here in the lab on an EVM that I could connect to the TSW1405 running the High Speed Data Converter Pro GUI.  I *am* able to power down channels on the ADC using register addresses 2 and 3.

    But, it looks like powering down a channel does power down that actual A/D converter for that channel but *not* the serialized output.  When I power down a channel I can see the current draw from the bench supply drop, from 225mA for the 3.3V supply and all channels active down to 61mA with no channels active.  When I write to registers 2 and 3 again to power up the channels, I can see the current draw go back to about 225mA. 

    When a channel is powered down, it looks like the serial output continues to output the last sample value that was from that channel.  I powered down channel 1 and the output was a constant value over an over.  The next time I powered down, the output was a different constant value.  Please see attached capture plot.   But since the LVDS output is active and outputting a value, there will be activity on the LVDS as seen on a scope as the output serializes the same code over and over.  It is not a static all-zero pattern.

    Regards,

    Richard P.

    ADS5270_ChA_Off_and_On.zip