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Nature of Data output

Shan Jaffry
Prodigy 80 points
Other Parts Discussed in Thread: ADS62P49

Dear all,

I want to ask about the nature of output from the ADC AD62P49 . Actually This is my first time using this type of ADC which is embedded with the FMC card.

I want to inquire that it works with X number of samples after 1 trigger... So does it gives all X samples accumatively after the trigger pulse or does it gives each sample per single clock given to the ADC. I have to store that data in the FIFO memory and I am using this assumption till now that each data sample I obtain at 1 clock cycle.

I also looked into the data sheet of ADC but could not get the proper idea.

waiting for your reply.

Bests,

Shan

  • 0
    TI__Mastermind 29220 points

    Hi,

    Figure 5 of the datasheet for the ADS62P49 shows the format of the sample output.  This device is not a triggered data converter - the device samples the analog input and outputs a digital sample with clock for every rising edge of the sample clock.  The output format may either be LVDS or CMOS, but in either case the output clock with the samples will be the same frequency as the sample clock and the format of the sample data is as shown as in Figure 5.  In the LVDS case, the data is DDR (dual data rate) where there are sample bits that need to be latched with both the rising anf falling edges of the output clock.  So there would be 7 LVDS pairs for the sample data - 7 bits bits of the sample are valid on the rising edge of the clock and 7 bits of the sample are valid on the falling edge of the clock.  In CMOS mode, there are 14 bits of sample data on 14 CMOS pins with data valid around the rising edge of the clock.

    So as you put it - the ADC gives a sample out for every sample clock rising edge given to the ADC.

    Regards,

    Richard P.