• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 409 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC5681(z) SYNC input: functional conflict when combining SYNC and TX_ENABLE function in one pin?

Koen Gadeyne
Prodigy 50 points
Other Parts Discussed in Thread: DAC5681

Hello,

The DAC5681(z) datasheet describes the "SYNC" input as being dual-use:

  • it must be '1' to enable DAC output. A zero on that input is stored in the internal FIFO along with the data and the DAC output is set to "0" when SYNC='0'. (chapter "LVDS SYNCP/N operation, page 39)
  • A '0' to '1' transition on the SYNC input is a "sync event" (chapter "LVDS SYNCP/N operation, page 39)
  • in fig 38, the text says that the SYNC input should be "1111" with an occasional "1101" for a SYNC event

What the datasheet fails to tell me is:

  • WHAT is synchronized with a "sync event"? The internal clock divider? The FIFO? more?
  • combining items 1 and 3 in the list above, I see a bit of a conflict: one one hand I'm told to insert the occasional '0' on SYNC to sync the device (=item 2 and 3), but on the other hand it also tells me that every '0' on SYNC will "blank" the output by inserting a zero (item 1).

I need a continuous output from the DAC with no gaps (no zeroes unless the data is zero).

SO what's up?

What happens when I insert the "occasional SYNC"?

  • WHat happens at the DAC output?
  • What happens inside the DAC (what gets reset, etc)?

Thanks,

Koen Gadeyne

  • 0
    TI__Guru* 78324 points

    Hi Koen,

    You are correct that the LVDS SYNCP/N functions as both TXENABLE and a sync event for the DAC's internal logics. When the LVDS SYNC transitions from 0 to 1, the DAC's internal FIFO and clock divider are synchronized. The FIFO needs a reset for the FIFO input/output pointers to line up correctly. The FIFO is often needed to create the buffer to relax timing requirement. Since this DAC is an inteprolation DAC, there are multiple divided-down clocks from a single clock divider to create the clocks needed for the interpolators. The sync event will align the starting phase of the divided-down clocks for optimal internal timing. Finally, after the 0 -> 1 transition, the SYNC will need to be held a 1 at all time for the DAC output transmission to enable.

    This occasional SYNC event is normally needed upon powering up the DAC to setup the DAC properly. Under normal circumstances, the FIFO and clock divider will run continuously without issue unless there are disruptive events such as loss of clock. Once the conditions are recovered, the DAC will need to be synchronized again by the SYNC signal. There is also a software sync if your application does not require multiple device synchronization. This may help you reduce a FPGA/ASIC IO. 

    In summary, the sync event is needed upon start-up. If there are disruptive events, the DAC will be to be resynchronized. 

    -KH