ADC14DC080 / frequency range for DCS

Here is additional information.

The unstable of DRDY means that the jitter on the output of DRDY appeared at 20MHz clock. There is no jitter at 40MHz clock input.

Best Regards,

The lower limit of the ADC14DC080 is the caused by the duty cycle stabilizer function, so you may be reaching a performance limitation at 20MSPS.

When you say 'Jitter' at 20MHz, what does the jitter look like in the spectrum? spurs or flat noise? Symmetric around a large fundamental tone? In-close (<10MHz BW) or far-out noise?

Have you tried using pin 19 OF/DCS to disable the DCS at 20MHz? How is the performance?

Regards, Josh

OH, jitter on the DRDY clock! What does the instability look like? Does the phase jump back and forth?

Please try turning the DCS off at 20MHz to see if this removes the instability.

Josh

Hi Josh-san,

Thank you for your comments.

I attached the waveform on DRDY pin with and without DCS. The input CLK were 20MHz and 50% duty.

They have not confirm analog performance with DCS, so I do not have information if the analog performance is gotten worse with this unstable DRDY output.

Best Regards,

Sonoki

Yes, it appears that the DCS is not stable for that device at the input clock frequency. If DRDY is so unstable that the data cannot be captured, then the remaining option is to turn off the DCS at the lowest clock frequencies and maintain a 50% duty cycle clock. At such a low clock rate, having the DCS active should not be critical as long as the duty cycle is not wildly off (70/30).

Hi Josh-san,

Thank you for your response. I'll recommend customer to not use DCS function with lowest clock frequency.

However it will be appreciated that we can inform why the DRDY output is unstable at lowest clock frequency with DCS, or recommended lowest frequency with DCS.

I believe that these information will prevent further trouble at customer side.

Best Regards,

Sonoki