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ADS7953: Meaning of "Source impedance needs to be 50 ohms or less"

Other Parts Discussed in Thread: ADS7953, OPA836, OPA835

I am trying to understand the meaning of the statement "Source impedance needs to be 50 ohms or less" in the datasheet for the ADS7953 ADC.

If I use a simple voltage divider on a 24V power source using a 5K ohm resistor and a 250 ohm resistor to get a 1.2V voltage value, can I tie this node directly to one of the channel inputs of the ADS7953 and switch channels every 1 millisecond without having to worry about the settling time / conversion errors?

Please advise. I can post my schematic and talk more in detail about my erratic values once I get an answer to this basic question.

Thanks in advance for your help.

BN

  • Hi Bob,

    We recommend using a low impedance source driver for the ADS7953 for accurate sampling when the part is running at fast sampling rates.

    The analog inputs to any SAR ADC are capacitive. Figure 59 (below) in the ADS7953 datasheet shows a model of the capacitive input for this part. The source impedance plus the capacitive input form an RC circuit which requires a certain amount of time to charge. If this time to charge is too long and the input of the ADC does not fully charge, the sampled voltage will be incorrect. Hence, we place a limit on the source impedance to keep the RC charging time short.

    In your application you have a larger source impedance, but you are also running at a lot slower data rate which usually allows more acquisition time to charge the ADC inputs. I believe for the ADS7953 that the acquisition time only increases if you use a slower clock (pulsing /CS less often does not gain you any acquisition time because the MUX will not change to the channel you want to sample until the 2nd SCLK falling edge, see the figure below). So depending on how you communicate to the device, you may or may not be providing enough time to charge the ADC input.

    A benefit to the ADS7953 is that the MUX output is brought out on the MXO pin. This allows you to use a single buffer for all analog input channels. The buffer has a high impedance input and low impedance output and so the ADC input charges much faster. (See the bottom of page 40 & page 41 in the ADS7953 datasheet, and the figure below). If you are having issues sampling the correct voltage, a simple op amp buffer such as the OPA835 or OPA836 connected between pins MXO and AINP may correct the issue.

    If you would like to share the details about the erratic values you are seeing, I would be glad to look into your circuit more.

    Best regards,

    Chris

  • Chris,

    This brings up a very important question:

    I am running my SCLK at 1 MHz and sending a manual-mode word every 1 millisecond that changes to the next channel and reads the previous channel's data back each time (I do the channel number checking on my 4 MSBs etc).

    DO I NEED TO PROVIDE SCLK CONTINUOUSLY BETWEEN CS ASSERTS?

    Right now, I take SCLK low when CS goes HIGH.

    How can I email/ftp a PDF of my schematic to you?

    Thanks.

    Bob N

  • Hi Bob,

    No, you only need to send a minimum of 16 SCLKS. Continuous clocking is optional; what you're doing is right.

    To send a schematic to just me you can start a private conversation with me on the E2E forum by doing the following:

    You can paste an image into the conversation or upload a file to our conversation. Usually uploading a file is much easier for me to view. Or, if you prefer, I can provide you with my email address once you start the conversation.

    Chris

  • Thanks, Chris.

    I just sent it to you.

    The ADS7953 circuit is on page 8.

    BN