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ADS5560 sampling clock edge

roger holden
Prodigy 10 points

Hello all, I am using this part to sample a video signal where the sampling point is critical.  The clkp input is AC coupled to an LVCMOS source (3v3) and clkm is AC coupled to VCM.  The data sheet indicated the sampling point is the posotive edge of clkp however during extensive testing it became clear the device is sampling on the NEGATIVE edge of clkp.

Further strange behaviour wrt to data sheet is output data changes shortly after negative edge of clkp and the output clock is a short negative going pulse with its leading edge shortly after the data changes.  I am running the device in low clock speed mode at 3.125Mhz, the input clock is continious, output data is LVCMOS and offset binary.

Any comments much apreciated!

Roger

I added this scope shot showing the input voltage, D14 output and adc clock to illustrate the problem (ignore ch4 its a trigger)

  • 0
    TI__Guru* 80765 points

    Hi Roger,

    I am currently working with your local FAE Patrick regarding this. So far, my lab measurement indicates that the sampling point is on the falling edge of the CLKIN as well. I am verifying this with our design team to see their feedback.

    Please see my response to Patrick:

    "After some experiments, I have also measured that the ADS5560 is sampling on the falling edge of the clock input rather than the rising edge. To simplify the test, I have set the input frequency to be the same as the clock frequency. I then align the input signal's phase to be either zero or full-scale at the rising edge of the sampling clock. The data output is maximum for zero and minimum for full-scale, and this indicates that theADS5560 is sampling on the falling edge of the clock input. 

    I have asked the design team in India to verify this also. If they confirm, we will need to change the datasheet to reflect this. 

    Regarding the comment about uneven duty cycle of the CLKOUT at low speed mode:

    •The uneven duty cycle at the clockout is normal for low speed mode. It is often easier to meet setup/hold time at lower clock rate than at higher clock rate. When the ADS5560 is clocked at less than 30MSPS, the device will need to be in low speed mode. At low speed mode, the internal delay lock loop (DLL) is disabled, and this DLL circuit is used at high speed mode to correct the CLKOUT's duty cycle for optimal setup/hold time of the data.
    •Even with non-50% duty cycle, the ADS5560 have a minimum setup/hold time on page 8 of the ADS5560 datasheet. This may be used as guaranteed setup/hold time for the FPGA when using CLKOUT as reference. Refer to attached PDF for diagram to see how low speed mode does not change the data valid window. "
    Please see attached .PDF file for more detail. Thanks
    -KH
    ADS5560_sampling_edge.pdf