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ADC12D1600 sample frequency

lei gong
Intellectual 600 points

Other Parts Discussed in Thread: ADC12D1600, ADC12D1000

I have a problem to consult  !

ADC12D1600 is a high speed A/D converter. If the input signal's frequency(VINI+/-,VINQ+/-) is 70MHz, and the sampling frequency is about 300M, relative to the chip of the ADC12D1600,the sampling frequency is low. Will it affect the performance of the chip ? I have the same question about DAC5670 .

Thanks !

  • 0
    TI__Mastermind 44680 points

    Hi Lei

    The ADC12D1600 (or ADC12D1000) will work very well down to the rated Minimum Sampling Clock Frequency (300 MHz with LFS=0b or 150 MHz with LFS=1b). Please refer to the Typical Performance Plots section of the datasheet. There you will find plots showing ENOB, SNR, THD and SFDR versus CLOCK FREQUENCY. You will see that the performance is quite stable across the entire range of sampling clock frequencies.

    I am not familiar with the DAC5670, so I'll let the experts on that product respond to that portion of your question.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Intellectual 600 points

    Hi Jim,

    Thanks for your help !

    Best regards,

    Lei

     

  • 0 in reply to lei gong
    TI__Genius 17470 points

    Hi Lei,

    The DAC5670 will work at 300 MSPS. At this low sampling speed the DLL will need to be disabled and the clock to data timing will need to be set appropriately by the FPGA. See the data interface external timing (with DLL in restart) section on page 9 of the datasheet.

    It sounds like most customers are using it at less than 1 GSPS. We do not have performance numbers at 300 MHz, however a plot of SFDR performance at 640 MSPS indicates that spurious performance does not change significantly over sampling rate.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Intellectual 600 points

    Hi Matt,

         Thanks for you help!

    Regards,

    Lei