ADS1292: when one doesn't need RLD, things to do with the driver...

Hi Bruce!

Can you provide us with the details of how you are setting the ADS1292 configuration registers?  Also, please let us know if you are testing with our ADS1292 evaluation board or hardware of your own.

Hi Tom, Register data below. It's our own hardware - working nicely for a bio-potential app, now using that platform to explore another application for the ADS1292. So I have been fiddling with the components that were in the conventional DRL circuit. Digital is 3.3V, analog 4.5V. Chip clock 524kHz. (for 512sps).

Comments to code may relate to the earlier biopotential app, but these are the settings I used to try for a half-rail buffered output...

In brief, RLD powered, internal reference, no signal channels connected.

[I'm not sure how to use the Offset_Cal, but that's a question for later.]

mov a, #ADS129x_WREG + ADS129x_CONFIG1 ;[b7:b0] SINGLE_SHOT 0 0 0 0 DR2 DR1 DR0 [000=128sps, 010=512sps]
 mov a, #00000010B ; PN: continuous, 500sps (512sps)

mov a, #ADS129x_WREG + ADS129x_CONFIG2 ; [b7:b0] 1 PDB_LOFF_ PDB_REFBUF VREF_4V CLK_EN 0 INT_TEST TEST_FREQ

mov a, #10110000B ; PN: no lead-off ,enable ref buf, Vref=4V, no clk out, no test sig

;mov a, #ADS129x_WREG + ADS129x_LOFF ;[b7:b0] COMP_TH2 COMP_TH1 COMP_TH0 1 ILEAD_OFF1 ILEAD_OFF0 0 FLEAD_OFF
 ;mov a, #00000000B ; PN: Fclk=512kHz + read-only status

mov a, #ADS129x_WREG + ADS129x_CH1SET ;[b7:b0] PD2 GAIN2_2 GAIN2_1 GAIN2_0 MUX2_3 MUX2_2 MUX2_1 MUX2_0
mov a, #01010000B ; PN: [7:]disable,[6:4] PGA=8x,[3:0] mux:no test sig

mov a, #ADS129x_WREG + ADS129x_CH2SET ;[b7:b0] PD2 GAIN2_2 GAIN2_1 GAIN2_0 MUX2_3 MUX2_2 MUX2_1 MUX2_0
 mov a, #01010000B ; PN: [7:]disable,[6:4] PGA=8x,[3:0] mux:no test sig

mov a, #ADS129x_WREG + ADS129x_RLD_SENS ;[b7:b0] CHOP1 CHOP0 PDB_RLD RLD_LOFF_ RLD2N RLD2P RLD1N RLD1P
 mov a, #00100000B ; PN: [7:6]chop Fmod/16 (8kHz), [5:]RLD enable (master!),
; [4:]RLD_Loff off,
; [3:0]no ch's derive RLD (master, ch2 can be disconnected, & depowered(?))

;mov a, #ADS129x_WREG + ADS129x_LOFF_SENS ;[b7:b0] 0 0 FLIP2 FLIP1 LOFF2N LOFF2P LOFF1N LOFF1P
 ;mov a, #00000000B ; PN: disabled

;mov a, #ADS129x_WREG + ADS129x_LOFF_STAT ;[b7:b0] 0 CLK_DIV 0 RLD_STAT IN2N_OFF IN2P_OFF IN1N_OFF IN1P_OFF
 ;mov a, #000000000B ; PN: b6:fclk=512kHz(default)

;mov a, #ADS129x_WREG + AADS129x_RESP1 ;[b7:b0] DEMOD_EN1 EN RESP_PH3 RESP_PH2 RESP_PH1 RESP_PH0 1 RESP_CTRL
 ;mov a, #000000000B ; PN: resp off (default))

mov a, #ADS129x_WREG + ADS129x_RESP2 ;;[b7:b0] CALIB_ON 0 0 0 0 RESP_FREQ RLDREF_INT 1
 mov a, #00000111B ; PN: Calibr off, resp freq=64kHz, RLDRef internal

mov a, #ADS129x_WREG + ADS129x_GPIO ;[b3:b0] GPIOC2 GPIOC1 GPIOD2 GPIOD1
 mov a, #00000101B ; GPIO1:I/P, GPIO2: as o/p (QWIZ Proto Link LED pn D2 XXX)

;mov a, #ADS129x_OFFSETCAL ; Cal bit in RESP2 needs to be set first
;lcall SPI_0_Write_Byte ; does it then need to be cleared?

Hi Tom,

Re: using RLD buffer as a half-rail driver,

The issue probably comes down to whether the RLD buffer is unity gain stable or not. First read of the ADS1292 spec sheet had me thinking it was unity gain stable since in the test conditions for the GBW Product spec it talks of G=1. But on a re-read, maybe that refers to the setting of the PGA.

thanks for the great support.

bruce

Hi Bruce,

You should be alright. How do you have the converter powered? Do you mind posting your schematic? If you do not want to have it posted public, you can send me a direct message and I will take a look and let you know some comments.

Regards,

Tony Calabria

Thanks Tony.

Still having grief. Quick question that might put me on the right track: Is it normal to be seeing 6.5V at Vcap2 ? (with 4.5V Avdd and 3.3V Dvdd)

With the drift I am seeing in the RLD circuitry, I suspect something is not connected right - in a couple of designs we have here.

[Not sure how to access you via direct message.]