• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 47 subscribers
  • Views 609 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AFE0064 linearity

Iolanda fuduli
Prodigy 60 points

Other Parts Discussed in Thread: AFE0064, ADS8363

Hi,

I'm using the AFE0064 as front end for a data acquisition system. i'm just at the beginning and I'm trying to understand the behavior of the chip. I'v got this output during my tests and it seems to be constant as I've ran the same test 4 times and I've always had the same output. The outputs look linear up to half scale then they become non-linear. I send in attachment a brief explanation of the setup and the problem that I have.Do yo have any hint about what I'm doing wrong?

 

Thank yo

Iolanda

AFE_test.pdf
  • 0
    TI__Prodigy 315 points

    Hi,

    Please mention the following in relation to figure 2 of the datasheet

    1) What is the value of t3?

    2) What is the clock speed?

    3) Are you in simultaneous mode?

    4) I am assuming the time delay between rise of SHR to rise of SHS is 14us. Is this correct?

    Regards,

    Nagesh

  • 0 in reply to Nagesh Surendranath
    Prodigy 60 points

    Hi Nagesh,

    thank you for your reply. So

    1) t3 is 448ns

    2) clock speed 2MHz

    3) I'm using the device in sequential mode. The final deign will have 2 AFE read by an ADS8363

    4) The delay you mention is actually 19us, 14us is the duration of INTG asserted high.

    please have a look in attachment at the timing from the CRO.

    Regards,

    Iolanda

  • 0 in reply to Iolanda fuduli
    TI__Prodigy 315 points

    Hi,

    The issue you are facing is because of the following reason:

    The AFE0064 samples integrator o/p at two time instances, one at SHR rise (say V1), the other at SHS rise (say V2). The AFE output is then 2*(V2-V1)-1.4V.

    The integrator o/p starts from 0.85V during reset and integrates linearly until the integrator o/p reaches about 2.3V. Beyond this, it becomes non linear and the intg o/p saturates close to the supply voltage, like in any amplifier.

    As the input current rises, both V1 and V2 rise and hence your AFE output increases. Beyond some value of input current, V2 saturates, but V1 continues to increase. So your AFE o/p drops. Beyond another value of input current, the V1 also saturates and the AFE o/p being related to V2-V1 responds very weakly to the input current. This is the reason for your observation.

    I am not sure if this is a problem for you, but if you wish to increase your linear input current range, you need to essentially reduce V1. For this, the time from end of reset to rise of SHR must be reduced as much as possible. Another option is to use the DDC series devices which are meant to cater to these applications, where essentially the above mentioned time is zero.

    Regards,

    Nagesh

  • 0 in reply to Nagesh Surendranath
    Prodigy 60 points

    Hi,

    I managed to have the linearity up to full scale increasing the delay SHR to SHS up to 100us, then it works fine. unfortunately I cannot reduce V1 due to the interface to the ADC. I hope that will work for our project. I know the series DDC, we will think about it, thank anyway.

    Rgard

    Iolanda