TSW3100EVM VHDL source code

Naresh,

The TSW3100 is a very old board and has been replaced with the TSW1400 board.

We have an application note that will publish very soon showing the DAC348x interface with a stratix IV on the TSW1400 capture card.  This application note includes the functional Quartus projects as well as documentation on how the system works.

Would you be interested in this application note which specifically highlights the Stratix IV and DAC348x interface?

Ken

Hi Ken C

I have TSW3100EVM and DAC3484EVM. I have to work with these EVM's.  I need to generate my own(custom) pattern. If I have TSW3100EVM VHDL source code that will be helpfull for me. If you have the code please send me.

As a engineer I am interested in the application note which specifically highlights the Stratix IV and DAC348x interface.

My E-Mail: nareshb@danlawinc.com

Naresh, We will send you what we have on the TSW3100 - keep in mind we cannot support any questions you may have on this older firmware - it is provided as is.

We will also send you the TSW1400 app note + project on the DAC34xx interface.  We can support you on this app note if you have any questions.  If you feel the TSW1400 is a better platform, it is significantly more affordable as compared to the TSW3100 and can be purchased from the estore for a very reasonable cost.

Ken

Naresh,

Attached is the TSW3100 source code.

Regards,

Jim

Hi Jim Seton

I see no attachment with the message.

Can you send the source code to my mail ID?

My E-Mail : nareshb@danlawinc.com

Thanks

Naresh

I WANT A CODE ,THANKS ! yin2332@sina.com 

Please see this link for TSW1400 Stratix IV project which shows connection of Stratix IV on TSW1400 to ADS4249 and DAC3482.

http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=slaa545

Ken.

I'm planning to drive ADS4249 using a Xilinx based platform.
Would that be different in comparison to Altera code provided in slaa545 ?

Hi Mostafa,

It will be different, but the concepts are the same. You'll require a DDR or input SerDes block to capture the data and then it's simply a matter of piecing the data together based on the specific block's timing diagrams. I think the following application note from Xilinx will be a great starting point for your project.

http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf

Regards,
Matt Guibord 

Hi Matt

Am I missing something here ? ADS4249 and a DDR bus , What does it have to do with SerDes Blocks?

I thought SerDes blocks is related to GTP banks !

Hi Mostafa,

I am not familiar with the Xilinx IP blocks, but for Altera there is an ALTLVDS block that is an LVDS serializer/deserializer (SerDes). This block can be used for more than 2x deserialization. There is also an ALTDDIO block that is used for DDR input data (2x deserialization). I believe Xilinx should have similar blocks.

Regards,
Matt Guibord