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DAC5687 Application design case - IF generation, BPSK Modulation

Moysis
Prodigy 50 points

Other Parts Discussed in Thread: DAC5687

Hello TI E2E Community members,

I am currently working in an RF project using the DAC5687 and I decided to open a design case in order to get some feedback from the community members who are more experienced on such applications. I will keep this post updated with results and waveforms in order to work as reference for others who are interested in similar applications.

In the application I am working on, I am planning to use the DAC5687 to perform BPSK modulation to a 1 Mbps bitstream. Result will be a 70 MHz IF frequency which will be later used for up-conversion to RF and transmission. The custom designed board I am using, connects only the CLK2, CLK2C pins of the device to the clock source which makes possible only the external clock mode. The external clock source is a PLL device which gives me the possibility to select among a variety of frequencies for clocking the DAC. 

Below I am summarizing some of my design decisions and some questions hoping for some feedback on them.

  • I select as clock frequency to the CLK2, CLK2C inputs the 131.072MHz. My other output of the PLL is 32.768 MHz  so it was convenient since it is an integer multiple of it. So FDAC= 131.072 MHz.
  • Next step is to establish the VCO frequency which will determine the IF. The exact IF I am aiming is 71.68 MHz. So FNCO=71.68 MHz. In the external clock mode FDAC=FNCO_CLK and we can calculate the frequency word. For the moment I don't bother with NCO Gain and the NCO Phase. I will experiment with them in the lab and I will post my results.
  • My first question is related to FIR Filter settings (Bits 5:4 of the VERSION register). Probably there is a piece of interpolation theory that I am missing here so any suggestion will be helpful.
  • Choosing an interpolation mode is also something that puzzles me. I have chosen the X4 mode but i am not sure if it is the most appropriate. The X4 mode results to a PLLLOCK frequency of 32.768MHz which is 32 times higher than the data bitrate. Since PLLLOCK is used to clock the data do you think that this can cause any issues? The fact that FDAC is much higher than the bitrate makes no interpolation mode suitable to produce the desired PLLLOCK frequency. 
  • In register Config1 I set Bit 4 high to enable 2's complement in the data interpretation. I found this the only way to achieve phase inversion of the NCO as required in BPSK. For example a bit '1' will be applied as "000000000000001". On the other side, a bit '0' or '-1' will be applied as "1111111111111111". That will have as a result only inversion of the NCO's Phase . Any suggetsions or recommendations about that would be useful too.
Regards,
Moisis
  • TI__Guru* 81485 points

    Hi Moisis,

    Regarding your questions to the FIR filters, you may refer to the High Speed Digital to Analog Converters Basics for more information. Basically, the FIR filters allows your interface rate to be slower while keeping the sample rate (DAC update rate) higher. 

    http://www.ti.com/lit/an/slaa523/slaa523.pdf

    Since your BPSK modulation is a 1Mbps bitstream, you may need to upsample this to 32.768MSPS sample rate before going to the DAC5687. The DAC5687's 4x interpolation filter will then upsample this again to 131.072MHz. 

    I am concerned about your NCO frequency. If you refer to page 36 FINE MIXER section, the NCO output is limited to -fs/2 to fs/2. In another words, the output of the NCO is limited to with the 1st Nyquist zone. If your NCO frequency requirement needs to be at 71.68MHz, you may need increase your CLK2 frequency (i.e. perhaps use x8 interpolation with CLK2 frequency of 2x 131.072 = 262.144MHz. Keep in mind the input data rate of the DAC still remains at 32.768MSPS. (i.e. 1/8 of CLK2).

    The 2's complement/offset binary configuration really applies to the input data format of the DAC5687 input. This set's the scale of the digital code whether to start from 0 to 65536 (offset binary) or start from -32768 to +32767. This has nothing to do with the phase inversion of the BPSK. The phase inversion will need to come from the data stream generated in the baseband. 

    -KH

  • Prodigy 100 points

    Hello,

    i want realize BPSK modulator using DAC5687,how to do inversion of the NCO's Phase i am not understanding.help me out

  • in reply to Nirmala Purighalla
    TI__Guru* 81485 points

    Nirmala,

    The DAC5687's NCO phase adjustment is often used to adjust the relative phase between two NCOs of two different DAC5687. It is meant to be adjusted only once at start-up/initialization of the DAC5687s. If this phase is adjusted during DAC transmission, the output may have transients from the reset of the NCO core and cause data error or even damages to the rest of the signal chain attached to the DAC.

    I am assuming you are asking about phase inversion of the BPSK differential encoding. This will need to be done on the data input side to the DAC5687 (i.e. the FPGA/ASIC attached to the DAC5687). Please let me know if I have misunderstand your question.

    -Kang