i configured the TVP7002EVM based on one of the default datasets to fit my needs, it seemd okay, and i saved that dataset.
i used microcontroller to set manually the TVP7002 and the THS8200 based on the saved dataset that i made.
the output display was awful, the colors was'nt right, and something about the sync seemed wrong.
ithen i tried to debug it manually, i found that when i change the value of register 0x15 in the TVP7002 from 04 (the value that the WINVCC4 saved in the dataset) to 06 (i figured it because i susspected that the Yb and cr were mixed), it seemed much better, but now i still got the sync problem, the output display was'nt sharp enough and it had green shadow.
after the long story, i got two question:
1. any idea what is wrong now?
2. is there any reason why a dataset that worked okay while using WINVCC4 is wrong while programming the registers directly?
i am adding the code that i wrote to the microcontroller to program the registers so you will be able to see the values that i use (this code is based on the dataset that i set):
WriteViaI2C(THS8200,0x03,0xC1); // chip_ctl
WriteViaI2C(THS8200,0x04,0x00); // csc_ric1
WriteViaI2C(THS8200,0x05,0x00); // csc_rfc1
WriteViaI2C(THS8200,0x06,0x00); // csc_ric2
WriteViaI2C(THS8200,0x07,0x00); // csc_rfc2
WriteViaI2C(THS8200,0x08,0x04); // csc_ric3
WriteViaI2C(THS8200,0x09,0x06); // csc_rfc3
WriteViaI2C(THS8200,0x0A,0x00); // csc_gic1
WriteViaI2C(THS8200,0x0B,0x00); // csc_gfc1
WriteViaI2C(THS8200,0x0C,0x00); // csc_gic2
WriteViaI2C(THS8200,0x0D,0x00); // csc_gfc2
WriteViaI2C(THS8200,0x0E,0x00); // csc_gic3
WriteViaI2C(THS8200,0x0F,0x00); // csc_gfc3
WriteViaI2C(THS8200,0x10,0x0C); // csc_bic1
WriteViaI2C(THS8200,0x11,0x00); // csc_bfc1
WriteViaI2C(THS8200,0x12,0x00); // csc_bic2
WriteViaI2C(THS8200,0x13,0x00); // csc_bfc2
WriteViaI2C(THS8200,0x14,0x00); // csc_bic3
WriteViaI2C(THS8200,0x15,0x00); // csc_bfc3
WriteViaI2C(THS8200,0x16,0x00); // csc_offset1
WriteViaI2C(THS8200,0x17,0x00); // csc_offset12
WriteViaI2C(THS8200,0x18,0x16); // csc_offset23
WriteViaI2C(THS8200,0x19,0x03); // csc_offset3
WriteViaI2C(THS8200,0x1A,0x00); // tst_cntl
WriteViaI2C(THS8200,0x1B,0x00); // tst_ramp_cntl
WriteViaI2C(THS8200,0x1C,0x53); // dman_cntl
WriteViaI2C(THS8200,0x1D,0x00); // dtg_y_sync1
WriteViaI2C(THS8200,0x1E,0x00); // dtg_y_sync2
WriteViaI2C(THS8200,0x1F,0x00); // dtg_y_sync3
WriteViaI2C(THS8200,0x20,0x00); // dtg_cbcr_sync1
WriteViaI2C(THS8200,0x21,0x00); // dtg_cbcr_sync2
WriteViaI2C(THS8200,0x22,0x00); // dtg_cbcr_sync3
WriteViaI2C(THS8200,0x23,0x00); // dtg_y_sync_upper
WriteViaI2C(THS8200,0x24,0x00); // dtg_cbcr_sync_upper
WriteViaI2C(THS8200,0x25,0x2C); // dtg_spec_a
WriteViaI2C(THS8200,0x26,0x58); // dtg_spec_b
WriteViaI2C(THS8200,0x27,0x2C); // dtg_spec_c
WriteViaI2C(THS8200,0x28,0x84); // dtg_spec_d
WriteViaI2C(THS8200,0x29,0x31); // dtg_spec_d1
WriteViaI2C(THS8200,0x2A,0xC0); // dtg_spec_e
WriteViaI2C(THS8200,0x2B,0x00); // dtg_spec_h_msb
WriteViaI2C(THS8200,0x2C,0x00); // dtg_spec_h_lsb
WriteViaI2C(THS8200,0x2D,0x00); // dtg_spec_i_msb
WriteViaI2C(THS8200,0x2E,0x00); // dtg_spec_i_lsb
WriteViaI2C(THS8200,0x2F,0x58); // dtg_spec_k_lsb
WriteViaI2C(THS8200,0x30,0x01); // dtg_spec_k_msb
WriteViaI2C(THS8200,0x31,0x00); // dtg_spec_k1
WriteViaI2C(THS8200,0x32,0x58); // dtg_speg_g_lsb
WriteViaI2C(THS8200,0x33,0x0C); // dtg_speg_g_msb
WriteViaI2C(THS8200,0x34,0x04); // dtg_total_pixel_msb
WriteViaI2C(THS8200,0x35,0x20); // dtg_total_pixel_lsb
WriteViaI2C(THS8200,0x36,0x80); // dtg_linecnt_msb
WriteViaI2C(THS8200,0x37,0x01); // dtg_linecnt_lsb
WriteViaI2C(THS8200,0x38,0x87); // dtg_mode
WriteViaI2C(THS8200,0x39,0x22); // dtg_frame_field_msb
WriteViaI2C(THS8200,0x3A,0x71); // dtg_frame_size_lsb
WriteViaI2C(THS8200,0x3B,0x71); // dtg_field_size_lsb
WriteViaI2C(THS8200,0x3C,0x80); // dtg_vesa_cbar_size
WriteViaI2C(THS8200,0x3D,0x00); // dac_upper
WriteViaI2C(THS8200,0x3E,0x00); // dac1_test
WriteViaI2C(THS8200,0x3F,0x00); // dac2_test
WriteViaI2C(THS8200,0x40,0x00); // dac3_test
WriteViaI2C(THS8200,0x41,0x40); // csm_clip_gy_low
WriteViaI2C(THS8200,0x42,0x40); // csm_clip_bcb_low
WriteViaI2C(THS8200,0x43,0x3C); // csm_clip_rcr_low
WriteViaI2C(THS8200,0x44,0x53); // csm_clip_gy_high
WriteViaI2C(THS8200,0x45,0x3F); // csm_clip_bcb_high
WriteViaI2C(THS8200,0x46,0x3D); // csm_clip_rcr_high
WriteViaI2C(THS8200,0x47,0x40); // csm_shift_gy
WriteViaI2C(THS8200,0x48,0x40); // csm_shift_bcb
WriteViaI2C(THS8200,0x49,0x40); // csm_shift_rcr
WriteViaI2C(THS8200,0x4A,0x8C); // csm_mult_gy_msb
WriteViaI2C(THS8200,0x4B,0x44); // csm_mult_bcb_rcr_msb
WriteViaI2C(THS8200,0x4C,0x00); // csm_mult_gy_lsb
WriteViaI2C(THS8200,0x4D,0x00); // csm_mult_bcb_lsb
WriteViaI2C(THS8200,0x4E,0x00); // csm_mult_rcr_lsb
WriteViaI2C(THS8200,0x4F,0xC0); // csm_mode
WriteViaI2C(THS8200,0x50,0x44); // dtg_bp1_2_msb
WriteViaI2C(THS8200,0x51,0x00); // dtg_bp3_4_msb
WriteViaI2C(THS8200,0x52,0x00); // dtg_bp5_6_msb
WriteViaI2C(THS8200,0x53,0x00); // dtg_bp7_8_msb
WriteViaI2C(THS8200,0x54,0x00); // dtg_bp9_10_msb
WriteViaI2C(THS8200,0x55,0x00); // dtg_bp11_12_msb
WriteViaI2C(THS8200,0x56,0x00); // dtg_bp13_14_msb
WriteViaI2C(THS8200,0x57,0x00); // dtg_bp15_16_msb
WriteViaI2C(THS8200,0x58,0x00); // dtg_bp1_lsb
WriteViaI2C(THS8200,0x59,0x00); // dtg_bp2_lsb
WriteViaI2C(THS8200,0x5A,0x00); // dtg_bp3_lsb
WriteViaI2C(THS8200,0x5B,0x00); // dtg_bp4_lsb
WriteViaI2C(THS8200,0x5C,0x00); // dtg_bp5_lsb
WriteViaI2C(THS8200,0x5D,0x00); // dtg_bp6_lsb
WriteViaI2C(THS8200,0x5E,0x00); // dtg_bp7_lsb
WriteViaI2C(THS8200,0x5F,0x00); // dtg_bp8_lsb
WriteViaI2C(THS8200,0x60,0x00); // dtg_bp9_lsb
WriteViaI2C(THS8200,0x61,0x00); // dtg_bp10_lsb
WriteViaI2C(THS8200,0x62,0x00); // dtg_bp11_lsb
WriteViaI2C(THS8200,0x63,0x6B); // dtg_bp12_lsb
WriteViaI2C(THS8200,0x64,0x58); // dtg_bp13_lsb
WriteViaI2C(THS8200,0x65,0x00); // dtg_bp14_lsb
WriteViaI2C(THS8200,0x66,0x5A); // dtg_bp15_lsb
WriteViaI2C(THS8200,0x67,0x00); // dtg_bp16_lsb
WriteViaI2C(THS8200,0x68,0x00); // dtg_linetype1
WriteViaI2C(THS8200,0x69,0x00); // dtg_linetype2
WriteViaI2C(THS8200,0x6A,0x00); // dtg_linetype3
WriteViaI2C(THS8200,0x6B,0x00); // dtg_linetype4
WriteViaI2C(THS8200,0x6C,0x00); // dtg_linetype5
WriteViaI2C(THS8200,0x6D,0x00); // dtg_linetype6
WriteViaI2C(THS8200,0x6E,0x00); // dtg_linetype7
WriteViaI2C(THS8200,0x6F,0x00); // dtg_linetype8
WriteViaI2C(THS8200,0x70,0x50); // dtg_hlength_lsb
WriteViaI2C(THS8200,0x71,0x00); // dtg_hdly_msb
WriteViaI2C(THS8200,0x72,0x01); // dtg_hdly_lsb
WriteViaI2C(THS8200,0x73,0x04); // dtg_vlength_lsb
WriteViaI2C(THS8200,0x74,0x00); // dtg_vdly_msb
WriteViaI2C(THS8200,0x75,0x01); // dtg_vdly_lsb
WriteViaI2C(THS8200,0x76,0x00); // dtg_vlength2_lsb
WriteViaI2C(THS8200,0x77,0x07); // dtg_vdly2_msb
WriteViaI2C(THS8200,0x78,0xFF); // dtg_vdly2_lsb
WriteViaI2C(THS8200,0x79,0x00); // dtg_hs_in_dly_msb
WriteViaI2C(THS8200,0x7A,0x00); // dtg_hs_in_dly_lsb
WriteViaI2C(THS8200,0x7B,0x00); // dtg_vs_in_dly_msb
WriteViaI2C(THS8200,0x7C,0x00); // dtg_vs_in_dly_lsb
WriteViaI2C(THS8200,0x82,0x5B); // pol_cntl
WriteViaI2C(THS8200,0x83,0x00); // cgms_header
WriteViaI2C(THS8200,0x84,0x00); // cgms_payload_msb
WriteViaI2C(THS8200,0x85,0x00); // cgms_payload_lsb
WriteViaI2C(TVP7002,0x01,0x42); // H-PLL FEEDBACK DIVIDER MSB
WriteViaI2C(TVP7002,0x02,0x00); // H-PLL FEEDBACK DIVIDER LSB
WriteViaI2C(TVP7002,0x03,0x58); // H-PLL CONTROL
WriteViaI2C(TVP7002,0x04,0x80); // H-PLL PHASE SELECT
WriteViaI2C(TVP7002,0x05,0x06); // CLAMP START
WriteViaI2C(TVP7002,0x06,0x10); // CLAMP WIDTH
WriteViaI2C(TVP7002,0x07,0x50); // HSOUT OUTPUT WIDTH
WriteViaI2C(TVP7002,0x08,0x80); // BLU FINE GAIN
WriteViaI2C(TVP7002,0x09,0x80); // GRN FINE GAIN
WriteViaI2C(TVP7002,0x0A,0x80); // RED FINE GAIN
WriteViaI2C(TVP7002,0x0B,0x80); // BLU FINE OFFSET
WriteViaI2C(TVP7002,0x0C,0x80); // GRN FINE OFFSET
WriteViaI2C(TVP7002,0x0D,0x80); // RED FINE OFFSET
WriteViaI2C(TVP7002,0x0E,0x24); // SYNC CONTROL 1
WriteViaI2C(TVP7002,0x0F,0x2A); // H-PLL AND CLAMP CONTROL
WriteViaI2C(TVP7002,0x10,0x58); // SYNC ON GREEN THRESHOLD
WriteViaI2C(TVP7002,0x11,0x40); // SYNC SEPERATOR THRESHOLD
WriteViaI2C(TVP7002,0x12,0x01); // H-PLL PRE-COAST
WriteViaI2C(TVP7002,0x13,0x00); // H-PLL POST-COAST
WriteViaI2C(TVP7002,0x15,0x06); // OUTPUT FORMATTER
WriteViaI2C(TVP7002,0x16,0x10); // MISC CONTROL 1
WriteViaI2C(TVP7002,0x17,0x00); // MISC CONTROL 2
WriteViaI2C(TVP7002,0x18,0x01); // MISC CONTROL 3
WriteViaI2C(TVP7002,0x19,0xAA); // INPUT MUX SELECT 1
WriteViaI2C(TVP7002,0x1A,0xCA); // INPUT MUX SELECT 2
WriteViaI2C(TVP7002,0x1B,0x55); // BLU AND GRN COARSE GAIN
WriteViaI2C(TVP7002,0x1C,0x05); // RED COARSE GAIN
WriteViaI2C(TVP7002,0x1D,0x00); // FINE OFFSET LSB
WriteViaI2C(TVP7002,0x1E,0x00); // BLU COARSE OFFSET
WriteViaI2C(TVP7002,0x1F,0x00); // GRN COARSE OFFSET
WriteViaI2C(TVP7002,0x20,0x00); // RED COARSE OFFSET
WriteViaI2C(TVP7002,0x21,0x0D); // HSOUT OUTPUT START
WriteViaI2C(TVP7002,0x22,0x00); // MISC CONTROL 4
WriteViaI2C(TVP7002,0x26,0x80); // AUTO LEVEL CONTROL ENABLE
WriteViaI2C(TVP7002,0x28,0x53); // AUTO LEVEL CONTROL FILTER
WriteViaI2C(TVP7002,0x29,0x08); // RESERVED
WriteViaI2C(TVP7002,0x2A,0x03); // FINE CLAMP CONTROL
WriteViaI2C(TVP7002,0x2B,0x00); // POWER CONTROL
WriteViaI2C(TVP7002,0x2C,0x50); // ADC SETUP
WriteViaI2C(TVP7002,0x2D,0x05); // COARSE CLAMP CONTROL
WriteViaI2C(TVP7002,0x2E,0x80); // SOG CLAMP CONTROL
WriteViaI2C(TVP7002,0x2F,0x26); // RGB COARSE CLAMP CONTROL
WriteViaI2C(TVP7002,0x30,0x27); // SOG COARSE CLAMP CONTROL
WriteViaI2C(TVP7002,0x31,0x18); // AUTO LEVEL CONTROL PLACEMENT
WriteViaI2C(TVP7002,0x34,0x29); // MACROVISION STRIPPER WIDTH
WriteViaI2C(TVP7002,0x35,0x00); // VSYNC ALIGNMENT
WriteViaI2C(TVP7002,0x36,0x00); // SYNC BYPASS
WriteViaI2C(TVP7002,0x3D,0x06); // LINE LENGTH TOLERANCE
WriteViaI2C(TVP7002,0x3F,0x0D); // VIDEO BANDWIDTH CONTROL
WriteViaI2C(TVP7002,0x40,0xF9); // AVID START PIXEL LSB
WriteViaI2C(TVP7002,0x41,0x00); // AVID START PIXEL MSB
WriteViaI2C(TVP7002,0x42,0x19); // AVID STOP PIXEL LSB
WriteViaI2C(TVP7002,0x43,0x04); // AVID STOP PIXEL MSB
WriteViaI2C(TVP7002,0x44,0x01); // VBLK START LINE OFFSET (F0)
WriteViaI2C(TVP7002,0x45,0x01); // VBLK START LINE OFFSET (F1)
WriteViaI2C(TVP7002,0x46,0x19); // VBLK DURATION (F0)
WriteViaI2C(TVP7002,0x47,0x19); // VBLK DURATION (F1)
WriteViaI2C(TVP7002,0x48,0x36); // F-BIT START LINE OFFSET (F0)
WriteViaI2C(TVP7002,0x49,0x37); // F-BIT START LINE OFFSET (F1)
WriteViaI2C(TVP7002,0x4A,0xE3); // 1ST CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x4B,0x16); // 1ST CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x4C,0x3A); // 2ND CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x4D,0x3B); // 2ND CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x4E,0xCE); // 3RD CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x4F,0x06); // 3RD CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x50,0x3E); // 4TH CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x51,0x3F); // 4TH CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x52,0x00); // 5TH CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x53,0x41); // 5TH CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x54,0x42); // 6TH CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x55,0xFC); // 6TH CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x56,0x44); // 7TH CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x57,0xF1); // 7TH CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x58,0x46); // 8TH CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x59,0x47); // 8TH CSC COEFFICIENT MSB
WriteViaI2C(TVP7002,0x5A,0x48); // 9TH CSC COEFFICIENT LSB
WriteViaI2C(TVP7002,0x5B,0x49); // 9TH CSC COEFFICIENT MSB