Other Parts Discussed in Thread: TVP5150AM1
I am developing a VITC time code reader/display (let's call it the 'VITC-Clock') for video production studios.
The VITC-Clock uses a TVP5150AM1 with a PIC32MX host processor, connected primarily via I2C.
The VITC-Clock reads VITC data from specific lines on the input video (either NTSC or PAL) and then displays HH:MM:SS on an LCD clock display. The VITC-Clock may also read the user data and use that for control or display purposes.
For my test setup I am using a DVD player for a video source (NTSC). A broadcast quality VITC generator superimposes time code onto the video signal. The output of the VITC generator goes into my prototype PCB. The VITC-Clock terminates the input video at 75ohms. The input to the TVP5150AM1 is about 500mVp-p. I am reading the VITC registers over I2C. I'm not using the FIFO. I2C rate is set for 100kHz for compatibility with other devices on the bus.
Initialization includes setting auto-switch video mode, initializing all the VDP line modes to 0xFF, then setting the C-RAM values per the data sheet at 0x160 and 0x170 with 16 values specified for NTSC VITC, full field mode disabled, and setting line mode registers for lines 10 and 12 both fields for NTSC-VITC with error correction (0x1B).
The TVP5150AM1 is detecting the NTSC mode, HSync, VSync, and CSync according to the status registers. It also signals that VITC data is available and I clear that bit (writing 1) immediately after reading each set of VITC data. I am polling the VITC data available bit every few frames, so don't necessarily read the data within the time of a frame (there could be several frames between reads) but the reading of the data and clearing of the data available bit happen right after each other.
Now I describe the problem...
Most of the VITC data is being read correctly by my application, but the 10s of hours byte and possibly the checksum byte are reading erratically. I have spent hours on it and haven't found the problem. The low nibble of the 10hours byte appears to shift between various values as though it is jittering back and forth. 0 in this nibble is always read correctly. 1 is read as either 0, 1, or 2. 2 is read as 1, 2 or 4. So the bit position sample appears to drift. The upper nibble is also affected roughly the same way. All of the other HH:MM:SS bytes appear to read correctly. (I'm not concerned about frame data).
As for the checksum byte, I am just doing a bitwise xor of all 9 bytes in the VITC payload and expecting that the result should be 0. It seems to rarely be correct, and even when I detect a packet with 0 result, the 10s of hours data is read incorrectly, so I think the checksum byte is being corrupted, too.
My input video source seems to be very stable, with the VITC payload stable wrt to HSYNC pulses. I have pretty much ruled out the problem being related to I2C errors, for example handling wait states as described in the date sheet. It seems to be the slicing of the VITC by the VDP.
I have tried changing the pixel alighment register from default 0x4E to either 0x4D and 0x4F. In each case the error was much, much worse, in fact most of the data was then corrupted. I find that effect strange when this value is described as defining the mode switch position between lines.
Please give me some ideas on how to debug this further!
Some things that could help are: a) to know the meaning of the values of the C-RAM data, b) to know how to check/scope the slicer bit clock in relation to the VITC data, c) anything else I need to know to set up the slicer, d) a description of how the slicer works in VITC mode.
Craig