• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 49 subscribers
  • Views 592 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1675 24-bit 4Msps ADC - How do you get 24-bits out per sample, serially, with a 32MHz serial clock, and reach 4 Msps?

JOHN MCCORKLE
Prodigy 150 points
Other Parts Discussed in Thread: ADS1675

I must be missing something!

On the ADS1675 24-bit 4Msps ADC - How do you get 4 Msps out, at 24-bits per sample, serially, with a 32MHz serial clock?

Seems like we need a 96 MHz clock. Even if it was DDR, we'd need a 48 MHz clock.

Thanks,

John

  • 0
    TI__Guru 55466 points

    Hi John,

    In order to be able to read the data at the maximum sampling rate, the user needs to read the conversions using the high speed LVDS (low-Voltage Differential Signaling) interface mode only.  An on chip PLL is used to multiply the input master clock CLK by three to be used by the serial inteface.  The data out, shift clock and data ready signals are output on the differential pairs of DOUT/DOUT, SCLK/SCLK and DRDY/DRDY. Page 23/ 24 provide some detail  and p7 provides the timing requirements. The document on the link below provides more information.

    http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slla014

    Thank you and Best Regards,

    Luis

  • 0 in reply to Luis Chioye
    Prodigy 100 points

    Hi Luis,

    The LVDS interface of ADS1675 is 1.8V or 2.5V?

    Thanks!

  • 0 in reply to jack zheng
    TI__Mastermind 23235 points

    Mr Zheng -

    Please see the Using LVDS OUTPUT SWINGS section (page 24) of the ADS1675 datasheet for more information on the voltage swings of LVDS interface.

  • 0 in reply to Greg Hupp
    Prodigy 100 points

    Hi Greg,

    I have read this section in datasheet, but I still cann't understand it. it says "The voltage on the outputs is centered on 1.2V and swings approximately 350mV differentially."But it didn;t say what kind of voltage standard should be used by FPGA, 1.8V, 2.5V or 3.3V?

    The other control interface of ADS1675 is 3.3V, so I will have to set the BANK voltage of FPGA to 3.3V. But the data interface is LVDS, can LVDS transmit through 3.3V standard?

    Thanks in advance!

  • 0 in reply to jack zheng
    Prodigy 100 points

    Anyone can help on this problem?

  • 0 in reply to jack zheng
    TI__Mastermind 23235 points

    Jack - 

    In looking through our offerings, you shouldn't have any problems using the interface with 3.3V.  You should also be able to run down to 2.5V as well.

  • 0 in reply to jack zheng
    Expert 1950 points

    Jack,

    even if your post is not the newest one:

    LVDS is an io-standard that is independant from the power-supply voltage used by the transmitter or receiver. As you wrote, a (differential) LVDS signal is always centered on 1.2V and has a differential swing of app. 350mV. This is true for all LVDS transmitter, independant of their power-supply voltage.

    For LVDS receiver, it's the same.

    This way, there are no compatibility issues interfacing e.g. ADCs using 3.3V power-supply with latest generation FPGAs using 1.8V power-supply. And this was also the reason why LVDS was defined in this way. The guys who developed the standard wanted to get rid of the dependancy between io-standard and power-supply.


    Regards,

    Niels