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Driving the ADS1256 with single-ended inputs

Damien Dusha
Prodigy 190 points

Other Parts Discussed in Thread: OPA2350, OPA350, ADS1256, THS4521, ADS1278

Dear all,

We have three single-ended sensors that are ratiometric to supply from 0-5V that we have interfaced to an ADS1256 via a OPA2350.  The OPA2350 is configured as a unity gain voltage follower, and the sensor is connected to VIN+ via a simple first-order RC filter.   The OPA350 directly drives AIN0 of the OPA2350 (not via a resistor or any other components).  This is repeated for each sensor, connected to AIN4 and AIN6. Each is referenced to AINCOM, which is connected to the same 2.5V reference that drives VREFP. The 2.5V reference is buffered by its own OPA2350 as per the recommended circuit in Figure 26 of the ADS1256 datasheet.

Typically, one sensor is at about 4V and the others at 1.5V.  On a scope, we can see the output of OPA350 of the 4V sensor dip by about 500mV for around 10ns and it takes around 20ns to fully settle (at least by eye). The power supply is stable during this time, as is the sensor output being fed into the op-amp.   The other channels, and the voltage reference also dip, by around 100mV or so.  Adding a capacitor (220N, low ESR/ESL ceramic) to the end of the OPA350 with the 4V signal reduces the dip to 100-200mV.

Is this normal and/or within acceptable limits?  Or, am I better off redesigning the buffer stage with something like a THS4521 that has a much higher bandwidth to drive the ADC?  Is there required to be a passive RC network (c.f. Figure 25 of the ADS1256 datasheet) that will help prevent the dip that I am observing on the scope?

  -- Damien

(Note: I have a similar and potentially related question on the reference circuit itself: See http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/218855.aspx)

  • TI__Guru**** 182601 points

    Hi Damien,

    Can you give us details about how you have the ADS1256 configured?  Sample rate, buffer on/off?  Can you perhaps share your schematic?

  • in reply to Tom Hendrick
    Prodigy 190 points

    Hi Tom,

    The ADS1256 is configured as follows:

      * Sample rate = 30KSPS

     * Buffers OFF

     * PGA = 2

     * Sensor detect off

    I have attached the relevant parts of the schematic that show the front-end and the ADC itself.  Thank you for taking a look.

      -- Damien

     

  • in reply to Damien Dusha
    TI__Mastermind 43915 points

    Hi Damien,

    When it comes to driving an unbuffered delta sigma converter, the cap at the input plays a crucial role for the sampling process. We do not necessarily show this cap or talk about it much in the ADS1256 datasheet since the device has the option to enable an internal buffer. You can think of the cap as a charge bucket for the sampling process. Now, the ADS1256 is different in that it has a built in PGA separate from the buffer so it is a little different than something where you are looking directly into a modulator, say the ADS1278 for example, but the concept regarding the cap should remain. Try enabling the internal buffer as a test first to see if the issue goes away which should tell you if the problem is lying in the modulation switching. If so, your design is going to require a capacitor at the ADC input. May I ask why you do not want to use the internal buffer of the ADC? I would think that it would be the easiest solution.

    Regards,

    Tony Calabria

  • in reply to Tony Calabria
    Prodigy 190 points

    Hi Tony,

    The buffer is off because the sensor signal (and voltage follower from the op-amp) swings between (almost) 0-5V. With the buffer on, it will only allow an input of (AVDD - 2.0) = 3V.

    We did solder a cap onto the end of the op-amp (220n, Murata LLL series - it's what I had lying around in a low-ESR series), and the dip whilst sampling/muxing reduced from 500mV to 100mV or so. It dips for around 10ns - 20ns.

    Nevertheless, I will enable the internal buffer to see if I still observe the dip in the signal.

      -- Damien

  • in reply to Damien Dusha
    TI__Mastermind 43915 points

    Hi Damien,

    Could you also use an oscilloscope to see the frequency of the dips. I'm curious if they are any way related to the modulator rate which would be an indication of the sampling switch. 

    Regards,

    Tony

  • in reply to Tony Calabria
    Prodigy 190 points

    Hi Tony,

    I have had a chance to take some measurements of the system.  I have tested with the buffer enabled and without - the results seem to be much the same. Please take the plots with a grain of salt - I am not entirely convinced that I'm not measuring ground bounce or something else unrelated.  Most plots are AC coupled so I can see the fluctuation, though you can also see them DC coupled.

    Note also, when I connect the input (VINP and VINN) to AINCOM via the input multiplexer, I get up to about 6bits of noise, which is consistent with Table 6, 30ksps, buffer off (which is 17.0 noise-free bits).

    Firstly, this is the plot that raises my suspicions about the system.  It shows the OPA350 driving the ADS1256 without any output cap.

    I didn't get a plot of it repeating, but it's consistent enough to trigger off it.  Repeating after it, it's at ~60ns, which is consient with each edge of the 8MHz clock.

    The OPA350 with the cap fitted has a much reduced spike, but there is some ringing on the output (though I cannot rule out that this isn't from a difference source)

    To try to determine whether the noise was from the clock or the modulator, the following plot is when the ADC is in standby mode (i.e. clock running, analogue should be off)

    Which it is, to some degree.  Though I did take another measurement a few minutes later with the following result:

    (Note 10mV per division, not 50mV per division), so there is some clock noise still there, but much reduced from before.The 5V rail looks very similar to this too.

    Placing the ADC into low power mode (i.e hold SYNC low, which turns off the oscillator) removes any identifiable clock noise at that frequency, though there is a small amount of residual switching noise at about 400KHz from the switcher that supplies the LDO.

    So, overall, I'm not sure what to make of it.  There seems to be a couple of things at play here.

      -- Damien