I would like to connect an ADC12DS105 to an FPGA via a HDMI connector.
The HDMI connector has 5 high-speed pairs, the ADC has 6 high-speed pairs (in 2-lane mode). Now the idea is to not use the OUTCLK signal, instead use the frame clock to create a high-speed clock with the PLL inside the FPGA to clock the data bits in.
Could that work? Any comments on this idea would be appreciated...
