This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

effect of amplifier open loop gain and ADC performance.

Other Parts Discussed in Thread: ADS4149, OPA690

Over the course of my career, I have learned that an op-amp must have an open loop gain greater than the number of bits of the ADC it is driving to prevent the effects of DC gain error (note: no the effects of GBW).  For example, a 14 bit converter should have an open loop gain >=2^14, or 16,384 V/V, or 84.3 dB.  Similarly, at 16 bits, the open loop gain should be >= 2^16, or  65,536 V/V, or 96.3 dB.  What I cannot find is how to determine the effects this has on an ADC perfromance.  i.e if I feed a 14 bit ADC with a "12 bit amplifier", what difference does it make to the ADC representation of the system input signal?

I have been looking around the literature for a while (here and other places) and have not found anything that directly addresses the question.

  • An addition:  I am trying to upgrade an old design from 12 bits to 14 bits.  The amplifier used in the 12 bit design is good for a bout 10 bits.  When I point out the issue of gain error, there is push back: "we have had no problems in the past, why change the amplifiers".  It may be that they did not know of the issue.  Also, it may be posssible to caligrate the error out of the system.

  • Fred,

    There are a number of issues to consider when selecting a driving op amp.  Take a look at this application note:

    Best regards,

    Bob B

  • This is very nice, with some nice guidelines, but it does not address the question asked.  Again, what is the effect of closed loop gain error of the amplifiers in a single chain on the bit accuracy of the ADC?

  • Fred,

    Here is some more reference information as it relates to op amp gain error.  You may find the most pertinent is Part 2.  I'm not sure that I'm still answering your questions.  As far as gain error prior to the ADC, this will affect the dynamic range relative of the incoming op amp error with respect to LSB size.  There are two components to consider.  One is the ideal gain and the other is a fractional component related to the inverse of the open loop gain.  If the open loop gain is very high relative to the closed loop gain, the effect will be less dominant.  Adding closed loop gain lowers the overall bandwidth, and this too must be a consideration relative to driving the ADC. 

    Part 1

    www.ti.com/lit/an/slyt367/slyt367.pdf

    Part 2

    www.ti.com/lit/an/slyt374/slyt374.pdf

    Part 3

    www.ti.com/lit/an/slyt383/slyt383.pdf

    Best regards,

    Bob B

  • Thanks Bob.  I think this is where I started.  I will look at this and see where it leads me.  BTW, you link to part 3 is taking me to part 2.

  • Fred,

    I fixed the link and it should work now.  One more thing to add is that open loop gain should be high enough to cover acceptable gain error with your system, but you don't use the op amp open loop, so you always need to consider the closed loop case.

    Best regards,

    Bob B

  • Thanks Bob.  I have read everything you have sent me, and I understand the sources and calculations of AC and DC gain error.  The issue is what is acceptable in my system.  This become an issue of how it effects the accuracy and dynamic range of the resulatant ADC output.  We will be using a TI ADS4149.  Our signal is band limited to about 32 MHz.  Currently it is being transformer driven by a OPA690 configured as an active low pass filter.  I don't think the OPA690 has sufficient OL gain, but there is push back (mostly because we use numerous other places and we would like to not bring in another part).  Even though I don't think the OPA690 has the OL gain, I do not know what improvement I might see if we go to a higher OL gain part.

  • Fred,

    Here is one more link you can go to and get some information that details a little more about gain error.  See Table 1 and the discussion on page 8.  As the open loop gain increases, the effect of error decreases.  With high bit ADCs you want to decrease the effect of the errorrelative to LSB size, so you want a higher open loop gain.  So a general rule of thumb has been to select open loop gain proportional to the number of bits.  As this only tells part of the story, most current recommendations discuss maintaining at least a 40 dB separation between the open loop gain curve and the closed loop gain for a desired frequency range.

    In your analysis of strictly open loop gain, I think you can come close to looking at about a 20dB difference between a 10 and 14 bit case.  Even though it is not correct to state the error as exact based solely on calculation, I think it is reasonble to look at the 80db case and the 60dB case from Acl = Aol/(1+Aol*B).  The difference doesn't amount to much until you start to add gain.  B = (1/Aideal).  It is at this point you need to maintain the desired safety margin difference between open loop and closed loop.  If you don't have much room to start with, then you cannot maintain adequate margin when adding gain.

    You may also, wish to get further detail with respect to the devices you are using by posting in the High Speed Data Converters forum.

    http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sloa035c

    Best regards,

    Bob B