• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 357 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12D1X00RFRB clock frequency

Brian Fisher
Prodigy 60 points
Other Parts Discussed in Thread: LMX2531

Hello,

I am using the ADC12D1X00RFRB board with the Wave Vision 5 software and I am have some difficulty changing the default internal clock frequency.  I would like to set it to 1830MHz or as close to that as possible.  The default clock frequency is 1590MHz and the eval board's manual says that the LMX2531 Clock Synthesis chip is configured for a frequency the range of 1530-1636MHz / 1726-1840MHz  through the serial interface which may be controlled through the WaveVision 5 register control panel.  Does anyone know which register is used to control this clock chip?

Thanks in advance for your help.

Brian Fisher

  • 0
    TI__Mastermind 44680 points

    Hi Brian

    If the board you have is operating at 1590 MHz it is the ADC12D1600RFRB, which is populated with the LMX2531LQ1570E PLL device. The device itself can support frequencies from 1530-1636 MHz but changing the frequency in the reference board environment is not practical. The GUI does not provide access to the PLL registers, and the frequency steps will be limited by the 60 MHz reference oscillator and the desire to use integer divider settings for optimum phase noise performance.

    To achieve 1830 MHz clocking with that board you will need to use an external RF frequency source and change the WaveVision settings to External Clock mode on the Register panel.

    If a bench type RF generator is used, it is important to follow the generator with a bandpass (ideally) or low pass filter to remove the harmonics from the clock. Even high quality, low phase noise generators will have significant 2nd, 3rd and higher harmonics on the output clock and these must be eliminated to achieve rated ADC performance. The generator and filter connections are shown in Figure 3 of the reference board users guide.

    I hope this is helpful.

    Best regards,

    Jim B

    (edited to fix a few typos, no content changes - Jim B)