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AFE7225 ramp pattern

Eduard Hasenleithner
Prodigy 20 points

Other Parts Discussed in Thread: AFE7225

I'm using the AFE7225 connected to an FPGA. In order to check the correct deserialisation of the ADC, I want to use the ramp test pattern. The data sheet says "D11..D0 ramps continuously every 4 clock cycles in steps of 1 LSB".

 With this description I would expect 4 identical values, and then the next value increased by 1. But what I get at the output is: D5..D0 ramps every clock cycle and D11..D6 ramps every 256 clock cycles. Is this just a omission from the documentation, or did I make an interface error?

  • 0
    TI__Expert 8895 points

    Hi,

    As the core pattern has 14-bit of resolution and the hardware interface of AFE722xEVM (AFE722x has 12-bit resolution) is aligned to MSB, LSB (Bit0) of AFE722x will be toggling every four clock cycle. And therefore the period of Bit1 is doubled from Bit0 (Measured frequency of Bit1 is a half of Bit0), and the period of Bit2 is doubled from Bit1 (Measured frequency of Bit 2 is a half of Bit1) and so on.
    LVDS or CMOS can be selected for the interface of FPGA and customers can choose 1-wire or 2-wire serial mode for the LVDS interface. Also these LVDS serial can be byte, bit or word wise mode. Depending on these configuration, deserialization processing from FPGA has to be implemented for the received data.

    If your clock cycles are the same every clock between D5 and D0, and the same every 256 clock cycles between D11 and D6, there must be something wrong with interface processing.

    Thanks,

    KW