Difficulties with the ADS8548

Christian Wolf

Other Parts Discussed in Thread: ADS8548

Hello,

I have a ADS8548 here serially connected to a FPGA. Now I have some questions related to the digital interface, as I am not sure if I understand the datasheet correctly:

My intension is to initalize the ADC and to verify everything worked well by reading out the config register.

Can I use a common serial clock for multiple devices? That means especially: Can I use an ongoing serial clock and just synchrinizing via FS? If no, the rest of the question is obsolet.

Is it allowed that the falling edge of FS and the falling edge of SCLK appear at the same time (this is my configuration, as the FPGA uses a state machine on the raising edge)?

As I have understood (and partly verified) the device outputs the MSB at SDO_x on the falling edge of FS. On every falling edge of SCLK the data changes to the next bit. That means I need the FS edge plus 31 SCLK edges. This makes approx. 31.5 clock clycles to read a ADC word. On the other hand I need 32 falling edges to latch all 32 bits. At the moment I just do not read the final bit from SDO_x, but I am not sure if this will trouble the ADC.

If I stop the SCLK while not transmitting data, the ADC behaves as expected and returns the corrct value of the config register. If I use continuous SCLK I get not the content of the config register. Rather I get something that looks like a conversion result (potentially old). I made some screen shots from my oszilloscope of the first transfer after power-up. The channels are from 1 through 3: SCLK, FS, DIN. You see first the total transfer, then the start of if (falling edge of FS) and the ending.

Can you tell me why the device does not answer correctly?

Thanks very much

Christian Wolf

over 12 years ago

0 Tom Hendrick over 12 years ago

TI__Guru**** 180751 points

Hi Christian,

The MSB of the ADS8548 is actually released with the falling FS signal - the subsequent bits are dependent on the SCLK. The intention for the serial interface mode was to run the SCLK in an SPI type fashion (clock stopped between transfers, dwelling high while inactive). Are you using the daisy chain feature of the ADS8548 or do you have multiple devices connected in parallel using the same serial clock?

0 Christian Wolf over 12 years ago in reply to Tom Hendrick

Prodigy 60 points

Hello Tom,

Tom Hendrick said:

The MSB of the ADS8548 is actually released with the falling FS signal - the subsequent bits are dependent on the SCLK.

You are talking of the SDO data pins or both inputs and outputs?

I am not using the daisy chain mode, as throughput is more important than number of lines. But it could happen that later on, both "channels" get daisy chained. But for now: two devices in parallel using the same clock.

If there is no alternative, in my application it is possible to synchronize the readout of the devices. So I can use a common clock either. But it would be more comfortable if it was not necessary. Then the question was: It is possible to start a new conversion, if a serial transfer is just running?

Thanks

Christian

0 Tom Hendrick over 12 years ago in reply to Christian Wolf

TI__Guru**** 180751 points

Hi Christian,

Sorry for the delay here - I was referring to the output data, the MSB on SDO is released with t_DMSB from the falling edge of the FS input (see Figure 1 on page 9). Ideally your host processor would begin to drive data into the ADS8548 at the same time, but the key timing on that side is having your data valid on the falling SCLK edge with the t_SUDI noted in Table 1. You could start a new conversion on one device while reading out another, I don't see where that would be an issue.

0 Tom Hendrick over 12 years ago in reply to Tom Hendrick

TI__Guru**** 180751 points

Hi Christian,

How is your project with the ADS8548 going?

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Difficulties with the ADS8548