Hello guys!
We are trying to connect our ADS1x7x EVM rev E (equiped with an ADS1274) to our FPGA. I'm a bit confused about which pins in connector J4 should be connected to our fpga dev board. We want to operate with Discrete FSYNC protocol, in HighSpeed mode. To achive that, we need FORMAT[2:0] = 101 and MODE[1:0]=00. Should I connect directly my FPGA pins to J4.8 (FORMAT[0]), J4.12(FORMAT[1]), J4.14(FORMAT[2]), J4.2(MODE[0]) and J4.6(MODE[1])? I saw in SBAU197 that those pins are connected to the ADS1274 pins and to U7 and U8 (TCA9535) pins. Drive J4.8, J4.12, J4.14, J4.2 and J4.6 directly can damage U7 and U8 ports?
We also want to feed the device clock (fclk) to ads1274, should I connect the clock source to J4.5 or to J4.17? Again, can I feed thos pins directly?
Any help will be welcome,
Thanks in advance,
Ronaldo