Trouble using DAC7562

Weird, my wave forms didn't show up. I'll try again. This one is data and clock.

This is sync and clock.

Tim,

The DAC7562 should power-up to zero-scale, that is the DAC output registers by default are loaded with 0x0000 by default. In your bus captures it looks like you turn on the reference, so unless there are more frames after the ones you've shown I wouldn't expect to see anything change on the output. Have you verified the presence of the reference output voltage? Or, does the reference voltage not turn on and this is your issue?

I checked the reference voltage at the pin. It sits at 0V.

I have even tried replacing the DAC, so I know that's not the issue.

Any updates?

Tim,

If you can share a schematic to augment your explanation of the circuit I would appreciate it. 

Right now it seems clear that the issue is hidden somewhere in your digital communication sequence since the reference voltage does not turn on. Things to look at in particular would be t1 (SCLK falling edge to SYNC falling edge) is at least 10ns, t5 (SYNC to SCLK falling edge setup time) is at least 13ns, t8 (SCLK falling edge to SYNC rising edge) is at least 10 ns, and verify the setup and hold times. Since you're running so slowly I suspect you're meeting many of these requirements but it would be excellent to have verification.

Here is an example of a successful write sequence enabling the internal reference:

Here is the schematic. The component on the left is a Molex header just so you know. 

Tim,

Lets try just keeping the DIN line high during the entire transaction. All of the bits for turning on the reference are 1s or dont care bits so this should verify functionality of your device regardless of if something unepxected is happening to cause a shift.

There are a total of 25 falling edges in your transaction so maybe removing the first one that happens before SYNC goes low would be a good test to make sure nothing is finding a way to get clocked in early. Just make the first thing that happens after SYNC goes low a SCLK falling edge. Verify all of the timing requirements, there is a little dither on the early SCLKs that makes the last 1 in the command word look like it may be close to the required setup time. In addition, if you can capture what's happening on the serial lines at power up that would be helpful to make sure that there isn't something damaging the serial interface.

The schematic looks fine, but I can't see what's happening on the VOUT lines. What you described before doesn't sound like it is a problem though.

I removed the first SCLK drop before SYNC goes low and made all the data bits 1s, but I am not getting a voltage on the reference pin. I have confirmed the timing requirements making sure there is plenty of setup time.

Because of the way I designed the PCB, there isn't an easy way to get directly onto the lines after the resistor (first time designing a PCB. This is quite the learning experience, haha). What I have noticed though using a voltmeter is that it sees 6V on the lines rather than the expected ~5.5V. This could very well be my problem by sending too high of a voltage on the lines thus damaging the ports.

Tim,

Any chance I can see the new bus transaction? Just want to make sure we're on the same page.

As far as designing the PCB goes, normally we include weak pull up resistors on the communication lines to keep them in a known and controlled state during power up. The worry is that while everything is turning on some transients could show up on the communication lines and put the device in an unknown state. Another good rule of thumb is to, if it's available, issue a hardware reset to the part once everything has powered up.

If the input is going up to 6V there is potential that the device is being damaged. When things violate the absolute maximum table there is little I can do to provide more insight than it 'may have' damaged the part.

What do you mean by "new bus transaction"?

Also, could you further explain how you set up the use of the weak pull up resistors? I -think- I know what you're talking about, but would like further explanation.

Yeah, I understand that it may have damaged it. I did i this way based on a recommendation because those diodes are supposed to have fast switch speed comparatively to a mosfet. I'm thinking it may be a better idea to run these switchable 12 V pins into the gate of a mosfet with 5V going through the channel to the clock, data, and sync pins. Your thoughts?

Here is the new capture.

Data is blue.

Sync is blue.

Hey Kevin,

I have another question for you. I've been looking through those level translators, but I'm having a heck of a time trying to find one that accepts a logic level 12V or higher as an input. Would you happen to know of one?

Hey Kevin,

I think I found one that would work for me, but I'm not 100% sure. I'd like to confirm with you first because I've never worked with these before: http://www.ti.com/lit/ds/symlink/cd4504b.pdf

I'm a bit worried about the power dissipation on that though because I don't want this getting super hot. Is it only 500 mW assuming every port is operating or is it a continuous 500 mW power dissipation? Is this even the right place to ask?

Tim,

The best place to find any in-depth familiarity with those devices would be the Voltage Level Translation Forum. I haven't attempted translating from such a high-voltage logic.

Alright, will do. You have been extremely helpful! Thanks so much for your help.

I have one last question about DACs before I go though. When connecting voltages up to the reference and power supply lines, should I add a resistor to prevent damage to the device from excess currents? Also, should I add resistors to the input lines for the same reason?

Tim,

Usually this is not a concern. The reference source / power supply source wont really push excess current into the device. The device will pull current based on it's active mode of operation. If something goofy were to happen in the circuit or had great potential to happen I could see a case for adding series resistance. The biggest problem/obstacle with doing such though is account for the voltage drop the series resistor would induce.

Yeah, I had the same initial thoughts, but didn't want to make any assumptions and break something again.

Thanks again, Kevin. You've been a lot of help.