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DAC7718 wrong output/offset

Other Parts Discussed in Thread: DAC7718

Hello there,

Im struggling a to get the DAC7718 running as i wish it to. I am using it in bipolar mode (+-12V supply, 3.3V Interface, 5V Ref, 4x gain, no correction engine). Power Sequencing for proper initialisation has been added (first 3.3 V, 1.5 sec later +-12V and further 0.5 sec later 5V Ref).

Im getting wrong output values as well as an incorrect offset voltages on REF-A/B. Both are approximately 4V, but according to the configuration it should be 3.333V.

For software communication i am using an SPI with 2x16 Bit transfers. According to the datasheet, if more than 24 Clk Cycles are applied during CS low, the last 24 will be used. So i am transferring 8 dont care bits, followed by the data bits. So this is my setup Routine:

 //Initialize DAC Peripherals

GPIOSetDir( 0, 20, 1 ); //LDAC_N

  GPIOSetBitValue( 0, 20, 1); //Init high

  GPIOSetDir( 0, 2, 1 ); //CLR_N

  GPIOSetBitValue( 0, 2, 1); //Init high

  GPIOSetDir( 1, 26, 1 ); //RST_N

  GPIOSetBitValue( 1, 26, 1); //Init high

GPIOSetBitValue( 1, 23, 1 ); //Set chip select high

// Write to Config Register

  GPIOSetBitValue( 1, 23, 0 );//Set Chip Select low

  src_addr[0]=0x0000;// 8bit don't care, 1bit Read/Write, 2bit Don't care, 5bit Target Register

  SSPSend( (uint16_t *)src_addr, SSP_BUFSIZE);

  src_addr[0]=0x8180; // 16bit Configuration

  SSPSend( (uint16_t *)src_addr, SSP_BUFSIZE);

  GPIOSetBitValue( 1, 23, 1 ); //Set Chip Select high

The following (for example) is used to set a output value

  GPIOSetBitValue( 1, 23, 0 ); //Set Chip Select low

  src_addr[0]=0x0008; // 8bit don't care, 1bit Read/Write, 2bit Don't care, 5bit Target Register

  SSPSend( (uint16_t *)src_addr, SSP_BUFSIZE);

  src_addr[0]=0xFFF0; // 12bit Data, 4bit Don't care

  SSPSend( (uint16_t *)src_addr, SSP_BUFSIZE);

  GPIOSetBitValue( 1, 23, 1 ); //Set Chip Select high

And afterwards a the LDAC_N pin will be dragged low for a short time.

 

I've added a PDF where you can see how the hardware was implemented (we are using the QFN-48 package, every peripheral with a pull up register can be pulled down by the CPU) as well as a plot of the DAC Output against different input values (represented in decimal values). As you notice, it should go from 0 => -10V up to 4096 => +10 V. But it actually goes down to around -11V, rapidly rises and then saturates around 4.65 V already at 1000 DEC.

5102.TISupport.pdf

 

Any help would be greatly appreciated,

kind regards

Alain

  • Alain,

    Have you tried reading back the offset register configuration to verify the digital values you anticipate are being written correctly?

  • Hello Kevin, thank you for your reply.

    Yes i did, the value is 0xAAB, just as mentioned in the Datasheet. I also read back the Configuration register, which as well seems to be as it should.

  • Fred,

    Your process here seems correct. I'd like to see oscilloscope captures of writing / reading data to a DAC output register, read / writing the configuration register, and reading the offset register. I just want to make sure that there isn't anything unexpected happening in your serial transaction since the schematic doesn't look to have any issues.

  • Hello Kevin,

    Thank you very much for your assistance.

    As you requested, i created plots of every Write and Read action you requested and also verified them directly by observation and program output.

    They are all correct. Every Readback matches the foregoing write command.

    6712.TISupport2_comp.pdf

     

    One more thing came to my mind. The Power Sequencing of the Ref Voltage is controlled by the boards CPU, which is ISP. So at the very first time the board was powered, the power sequencing was only aviable for 3.3 and +-12V, the ref voltage came up immediately after +-12V (VRef is powered by 12V). Is it possible that this damaged the DAC7718 IC?

  • Fred,

    I'm a little stumped on this. I'll have to take a board into the lab and try to replicate things and see what 'gotchas' I might bump into.

    One concern I do have is the noise on CS and some of the other clock signals. It's hard to say if this was how you probed the bus (GND clips not connected, etc) or if these artifacts are actually appearing on the bus.

  • Fred,

    One item that is worth looking into is reducing the reference voltage. There is a small note on page 5 below the electrical characteristics table that specifies that the reference input voltage must be less than DVDD. If this condition isn't met I could see some potential to damage internal components to the device that may have damaged the resistor string and create the output trend you've observed.

  • Kevin, you are my hero!
    We tied DVDD and IOVDD to 5V and now it works wonderful. Right in time, since the deadline is drawing near.

    I am going to build an altar for you and afterwards ill sacrifice an animal of your choice on it.