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how to clock the ADS809 data into sync register

John Mladenik
Intellectual 280 points

Other Parts Discussed in Thread: ADS800, ADS900, ADS820, ADS4125, ADS6125

Does the DV signal clock continuously and so can be used as a clock? 

I need to clock the output data of the ADS809 into an IOB register of an FPGA and then from there to an internal FIFO or DSP module.    What is the relationship of the DV (Data Valid) signal to the CLK?, that is no clear in the data sheet.   Also there is no description on how the DV should be used to clock in the data.  DO you ahve an example schematic the clocks the output of the ADS809 ito a sync FIFO?

 Should I use the DV to clock the data in or the clock signal itself.   Can I use DV ='1' as an enable to the flip flop when clocking the data in with the clock?  If so I need to have the worst case timing between the edges of the clock and of the DV.  

I will be performing some DSP on the data and only want valid data to be clocked into the FIFO.     

  • 0
    Intellectual 280 points

    It looks to me that I can use the falling edge of the DV as the clock?  If so what are the worst case timing from the data changing to the falling edge of DV?   Whatever edge of whichever clock I use I need the worst case timing from that edge to the changing edges of the data to insure worst case timing of the design.  

  • 0 in reply to John Mladenik
    TI__Mastermind 29220 points

    Hi,

    On that generation of devices, the digital data was generally expected to be clocked into an FPGA or ASIC using a copy of the same sample clock that goes to the ADC itself.  I don't see an EVM specific for the ADS809, but EVMs for similar devices such as ADS800, ADS820 or ADS900 generally had a copy of the sample clock going to the connector with the digital data.  But then the DV signal was not always present on some of those devices.  It looks to me like the DV signal would be latched along with the digital data as just what the name implies - indicating that the data is valid.  It may be possible to use an edge of the DV signal to do the latching, but I need to look at the datasheet some more.  As far as additional timng information, what is in the datasheet is what I have as well.  This is an older device from an acquisition so we do not have additional information from device characterization to look at. 

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 280 points

    I have spoke with 2 other engineers who used this part and they both used the DV to clock the data in(Not sure what edge they used).    My initial design did exactly as you said using a version of the CLK to clock the data in and using DV to enable or as a DATA Valid, but I do not see the timing parameters I need to constrain the FPGA in a way to guarantee it meets timing.   What is the min/max time from the rising edge of the DV to the rising edge of the clock.  Or the MIN/MAX time from data change to the rising edge of the CLK?

    Is there a newer better TI ADC with the same analog specification that may have a better defined digital interface?    

  • 0 in reply to John Mladenik
    TI__Mastermind 29220 points

    Hi,

    From my reading of the datasheet, the data typically becomes valid 9ns after the sample clock and the rising edge of DV is typically 10ns after the sample clock.  Or looking at the max numbers, the new data becomes valid by 11ns max after the sample clock while the rising edge of DV comes at 12ns max after the sample clock.  So it looks to me like the rising edge of DV could be used to latch the data with about 1ns setup time and lots of hold time.  The question then becomes is this guaranteed - in other words could the data possibly take the max time to appear when the DV edge takes typical or less?  The data sheet does not tell me, but I would expect these timings to be strongly correlated since buffer delays on silicon tend to track supply, temp and process parameters the same way.  So I am guessing they would have used the rising edge of DV.   I do not have more data available than what I see in the datasheet. 

    Over time our datasheets for new products become more and more complete, and a new datasheet would never be this sparse on the specification of the output timing.  So I would say that all our newer devices have a better defined digital interface.    Most of our newer devices output a true clock with the data and will guarantee the timing of the data around the clock edge.  For example, ADS4125 or ADS6125 would be a 12bit ADC with operation up to 125Msps.  These devices can output single ended CMOS data like the ADS809 or they can output LVDS data. 

    But before an alternate device could be specified, we'd need to know how many aspects of the ADS809 are important to you besides number of bits and sample rate.  For example, the older devices like ADS809 would often accept single ended analog input with the other side of the analog input tied to mid-rail.  The newer devices require a differential analog input.  The newer devices often have a longer internal pipeline delay in getting the sample out of the ADC which might become important in a feedback-loop type of application.  So I would suggest taking a look at the ADS4125 and see if that type of device definition fits your application.

    Regards,

    Richard P.