ADS1259 without buffer at input

Hi Bob,

Thanks for answer.. However, so as not introduce noise into system we want to use 2nd order LPF as well. We want to drive the ADC directly through it. This will require 100K and 0.22uF components. However this will not satisfy the settling time criteria of 0.5 us. (given FLCK= 7.3728MHz, Serial CLK = 1MHz, sampling rate = 50 SPS & reference of 3V and power supply of +5V and 0V)

How to satisfy the settling time criteria?

Regards,

Vinayak

Hi Vinayak,

You've added a significant new issue from your first post.  You have now gone from a current divider to a voltage divider.  For my first response all that was needed was a simple RC anti-aliasing filter (approximately 50 ohms and 10nF.)  If the desire is to create a low frequency filter, and if you add large resistance values you move from a simple current divider to a voltage divider.  Also settling time will be very large.  With a 24 bit converter your settling time will be related to resolving to 1/2 LSB.  If you have a large time constant this may be problematic if your input signal changes often and quickly.

There are trade-offs.  What level of noise can you accept and what resolution is required?  If you need the low frequency filtering, you will need a buffer.

Best regards,

Bob B

HI Bob,

I had tested the 10nF and 47 ohm resistance filter, but i did not get expected result. I have also tested RC LPF (100K & 0.22uF) connected before ADC inputs..Still did not get expected results. I am using cut off frequency of 7 Hz. Input direct current is 4-20mA. Still I need buffer?   Also I did expect 10nF and 47 ohm filter could work for ADC, but it did not. Have you any thoughts on probable cause?

Regards,

Vinayak Aghor

Hi Vinayak,

If you use a series resistance of 100k, you will need a buffer.  When you say you did not get the expected results, what do you mean?  What were the test conditions?  What did you expect and what did you get?  I can try to duplicate your setup, but I need more information.

Best regards,

Bob B

HI Bob,

With 47 ohm & 10nF cap filter I got ADC count as: (here i have shown first 16 bits from MSB)

4mA --  0x0C07

12mA – 0xE0C0

 20mA – 0xF424

I expect ADC count as

4mA --  0x2CCA

12mA – 0x8E89

20mA – 0xE826

Test conditions : I am giving 4-20mA current across 130 ohm resistor and then giving it to RC filter & then giving it to ADC input. Even if I use RC LPF filter of 100K and 0.22uF then connect it to ADC inputs, i did not get expected results.

With 47 ohm and 10nF filter, time constant of 0.47us which is around 1/ (Fmod/2) = 0.5us. Input needs to settle within 0.5us.

what should be the cause or remedy to get expected result?

Regards,

Vinayak Aghor

Vinayak,

The data from the ADS1259 is binary two's complement.  I think there is something wrong with your calculations and perhaps read back of the data.  You should only be seeing codes from 0x000000 to 0x7FFFFF, unless you are adjusting the gain calibration register.  Can you show me how you are making your calculations?

Your settling time is relative to the analog filter settling to 1/2 LSB size.  This is the time that it takes for a step change voltage to respond at the output of the filter to within 1/2 LSB value. LSB size is full-scale range divided by 2^24 bits.  This will be many time constants, so you can see that if you increase the time constant it will take a very long time for the analog input to settle.

Outside of a calculation error,  you may not be seeing the circuit settle.  Are you taking multiple readings at each current level, or are you taking single point measurements?

Earlier today I took some measurements using slightly different resistance (200 ohms) and current levels from 4 to 10mA, and had measurements very close to the expected and quite linear.  There was some gain error as expected.  I will try to capture some data and send you my results.

Best regards,

Bob B

6724.calc.xlsx

Hi Bob, I have inserted calculations in file. I can see that gain error of 2 is present in the counts. Please let me know if there is wrong in procedure. in file 1 table calculates ideal count and second table calculates current from count. we are considering first 16 bits of ideal count.

you can change current and ADC count that you got in sheet, and compare results.

For settling time, you suggest , around 350ns can be ideal settling time (=3V / 2^24). Is it correct?

i am taking multiple readings however ENOB that is considered is 16, we do not need to average the ADC count.

Also i have kept some margin of 3mA more. So 0x7FFFFF will be at 23.07mA

Regards,

Vinayak

Vinayak,

Settling time will be approximately 12 time constants for 16 bits and about 17 time constants for 24 bits for analog settling.  I'm sorry but I've been rather busy today, so I haven't had time to fully analyze the spreadsheet but it appears that your initial calculations are correct.

It also appears that the calibration constant in the FSC register is forcing a gain of 2.  I will have to check into this a little further on my end to fully understand what might be happening.  Are you doing any offset or gain calibration? 

Best regards,

Bob B

Hi Bob,

Kindly tell us how you calculated 12 time constants figure. should i figure out 12 times less than sampling time for internal capacitor of 8pF+2pF?

it comes out as 1.1us / 12.  1.1us comes from 1/Fmod.I will choose external RC filer of time constant of 90ns. is this you are suggesting?

I do not want to calibrate the system. I am jest reading raw data.

Regards,

Vinayak

Hi Bob,

when I connect 130 ohm resistor to ADC input with 10nF cap across ADC inputs the I get expected ADC counts with some acceptable offset and gain error.

Here i did not use anti-alias filter before ADC inputs. This is the real problem.

Regards,

Vinayak Aghor