Hi-
running an ADS1298 on a SPI bus that is also used by other components.
The datasheet says on page 28: "When CS is taken high, the serial interface is reset, SCLK and DIN are ignored" and on page 30: "Note that DRDY goes high on the first falling edge SCLK regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin."
Now, I do see that the DRDY indeed goes high whenever there is activity on the SCLK signal, regardless of the status of the CS pin (i.e., even with CS/ = 1, a SCLK signal will make DRDY/ go back high). This can in my case lead to a zero-length DRDY signal screwing up the entire timing.
Question: is there an ADS1298 configuration setting that would let the DRDY go high only on SCLK pulses while CS is low?
Looking forward to your answer :)
Bernhard
