• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 48 subscribers
  • Views 501 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1298 initialization question

Todd Anderson78572
Guru 14640 points
Other Parts Discussed in Thread: ADS1298, ADS1296

All:

Here is a quote from the ADS1298 datasheet, p.34, paragraph Reset:

"Note that an internal RESET is automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to new values with a WREG command."

When intializing the ADS1298, it looks like after writing to CONFIG1 or RESP, you must then wait 18 Tclk cycles for the reset to be finished, correct?

So an init sequence would be:

1. Read ID

2. Write CONFIG1 (assuming a different setup than default).

3. Wait 18 Tclk cycles.

4. Read CONFIG1 (to verify).

5. Using a loop, (write/read) registers CONFIG2 thru PACE (0x1 to 0x15).

6. Write RESP (again assuming different than default).

7. Wait 18 Tclk cycles.

8. Read RESP (to verfiy).

9. Using a loop, (write/read) CONFIG4, WCT1, and WCT2.

Does that look like a proper way to initialize the part?

 

  • 0
    Prodigy 215 points

    Hi Todd,

    I read that paragraph a little differently - i don't think you need to wait 18 tclk cycles to verify what you have written to (for instance) the CONFIG1 register - it takes that long for all registers to settle to their default values.  The Digital Filter reset I believe has to do with the paragraph a little further down on that page in the data sheet regarding the settling time.  I don't see where your proposed initialization sequence would be a problem though.

  • 0
    TI__Guru**** 180961 points

    Hi Todd,

    Happy New Year!  Has this been resolved or do you still need some clarification on the ADS1298 setup?

  • 0 in reply to Tom Hendrick
    Guru 14640 points

    Tom:

    I would like to know if I need to put in a wait of 18 Tclk cycles as mentioned above - as in step 3. If not, I will not include that.

    Also, on an ADS1296, do I treat channels 7 & 8 like I would treat an unused channel? For instance, should I set the Power-down bit for channels 7 & 8 like I would for an unused channel?

  • 0
    TI__Mastermind 43915 points

    Hi Todd,

    I would be happy to answer your questions you have. I agree with Nicholas in that I do not see anything wrong with your write sequence. I do not believe you need to wait the entire 18tclks after each write to set the registers. The tSDECODE time (4tclks) is the restriction on how fast you can write to update the registers. This requires that there is a minimum of 4tclks between the 8th SCLK of each byte transfers to allow for each 8 bit command to be decoded properly and the register set appropriately. The 18tclks has to do with the digital filter resetting following any sort of RESET (command or pulse of I/O line). Of course, waiting 18 tclks after each write is not going to be a problem so your initial sequence would be fine as is also.

    You are using the ADS1296 where the converter does not include a channel 7 or 8. In that case, you can treat those channels as usused and their registers will be fixed in power down mode. You will want to pull the analog input lines for the unused channels 7 and 8 high to the AVDD supply through weak pull up resistors.

    Let me know if you have any further questions.

    Regards,

    Tony Calabria