As shown in figure, we use the first NAND gate of CD54HCT00F3A receive signal(the input of width 1.6 u s, voltage of 4.8 V pulse signal), pin 5 always 5 V high level, the output of the second NAND gate as a chip select (Low Level effective). we use the signal generator produce frequency of 312.5 KHz signal to pin 1, the pin 6(CS)should be output 312.5 KHz low level, with an oscilloscope observation but always at a high logic level. Adjust the signal generator frequency to 2 KHz and below, pin 6 (CS)output is normal, excuse me, may be what leads to failure?
