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ADC integer to volt conversion

Shan Jaffry
Prodigy 80 points

Dear all,

I am using 14 bit ADC(AD62p49 with LVDS mode) to acquire data and the data is acquired correctly but I am capturing the
data through C++ code and hence capturing it in 16-bit short integer with left justified.

Now the problem is I have to convert it back to the volts and I think if I divide by 2^15 (MSB is sign bit).
but the value that I get is not correct.

Any experience for this conversion.

Bests,

Shan

  • 0
    TI__Genius 17340 points

    Hi Shan,

    Are you capturing offset binary or 2's compliment data? Are you able to plot the raw codes to verify they are correct in the time domain?

    If it is 2's compliment and left justified, then dividing by 2^15 seems correct.

    Can you share your data?

    Regards,

    Matt Guibord 

  • 0 in reply to Matt Guibord
    Prodigy 80 points

    Hello Guibord,

    I am using 2's compliment and yes I draw the integer values using origin and have verified that the signal is correct since I obtained the desired waveform(s).

    I have shared the file. Please verify it.

    Can I ask two more question...

    1. what if I also add 6db attenuator at ADC input? Do I also have to multiply by 3.98 (equivalent to 6db)

    2. If you plot the file, you will notice that there are final 15 samples just trash...I have tried many things to rectify it, but could not. Any suggestion

    (by many things I mean to change the tap delay values of FPGA many times)

    Thank you for response

    Bests,
    Shan
  • 0 in reply to Shan Jaffry
    TI__Genius 17340 points

    Hi Shan,

    Do you expect this small of a signal? I plotted it out and saw something that looks like an "event" but I'm not sure what you're expected. Have you tried applying just a sine wave to verify correct functionality? Note that the input is AC coupled by transformers which will prevent low frequency signals from passing.

    You can easily calculate the voltage at the ADC pins as previously mentioned. If you want to calculate the voltage at the EVM input you would need to account for the losses in the transformers as well as any attenuation you've applied.

    I am not sure what the 15 samples are from. Do they occur during every capture? At the same location?

    Regards,
    Matt Guibord 

  • 0 in reply to Matt Guibord
    Prodigy 80 points

    Thank you Matt,

    Actually this is not small signal, It looks veeery small because of the large negative pulse at the end and it is unwanted signal. It is not the actual part of signal but when I change the sampling frequency I am not getting this thing as well. I want to remove this sooner or later, do you have any idea about that as well.

    Yes I have tried using the sine wave as well. It is coming completely all right witht he exception that the last negative spike also appears unwanted...

    What is this by the way.

  • 0 in reply to Shan Jaffry
    TI__Genius 17340 points

    Hi Shan,

    I do not know what the negative spike is. I can assure you that this is not coming from the ADC. Are you using one of our pattern capture cards (TSW1200, TSW1400, TSW1405) to capture the data? Or is this your own FPGA code?

    Regards,
    Matt Guibord 

  • 0 in reply to Matt Guibord
    Prodigy 80 points

    Thank you for your reply.

    I am using 4DSP board and it utilizes AD62p49 model ADC.

    Yes the FPGA is integratedwith ADC to acquire the data.

    Bests,

    Shan

  • 0 in reply to Shan Jaffry
    TI__Genius 17340 points

    Hi Shan,

    My guess is that you have a certain buffer size that you start filling up based on a trigger and then you read the data back. If that's the case, I'm guessing your trigger is triggering prematurely (by 15 samples or so) or something to that effect.

    Regards,
    Matt Guibord