• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 262 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

dac3482 sampling rates and bandwidth

Arvind Bhat
Prodigy 235 points
Other Parts Discussed in Thread: DAC3482, DAC3484

For the DAC3482 the maximum fdata is specified as 625MHz in word-wide mode. i am slightly confused with the clocking architecture shown in Figure 53 (Fifo block Diagram) of the datasheet. If fdata is 625Mhz, then the FIFO input "Dataclk" is operating at 625Mhz DDR mode. That is shown correctly. But why is the output side clocked at dacclk/2/interp in word-wide mode ?  Where does the extra /2 factor come from ? If the dacclk is maximum at 1250MHz, then the fifo output will be clocked at 312.5MHz which is a clocking rate mis-match. Am i missing something here?

Also, i am working with the DAC3484. The register map does show option for "dual channel mode" operation (config1 and config16 registers). I have never used this option, but when programmed for dual mode, is the dac3484 exactly compatible with dac3482 ? Are there any differences?

thanks,

AB

  • 0
    TI__Guru* 78164 points

    Arvind,

    The clock rate difference is due to the FIFO operation in word wide mode, and the user do not need to worry about this since this is all taken care by the device itself.

    You are correct that the dual channel mode of the DAC3484 is functional equivalent to the DAC3482.

    -KH