AFE7222 clock input level requirement

Hello,

First of all, I'd like to ask how you tested AFE7225EVM with J18 (CLKIN). For this clock input, you have to modify EVM hardware. Otherwise, it won't work. The default clock input is to use J10 for CDCE72010.

Have you got a chance to measure VCM of AFE7225?  The typical value of VCM is 0.95V.

Thanks,

KW

Hi KW,

I did modify the EVM hardware so that I could use J18 to input a clock from our signal generator. I removed R76 and installed R74, R77, and R112. Then I connected our RF signal generator to J18 and varied the signal amplitude while measuring the signal level with a scope probe at R88 (which is not installed).

I could also see the VCM on the scope as I measured the clock signal right on the AFE7225 pin. If the input signal level is sufficiently high then the VCM is about 0.95V as expected. If I set the clock amplitude to the level we have on our board (from LVDS clock buffer) and then power up the AFE7225EVM, the VCM on the clock input is 0V. If I increase the clock amplitude at some point the VCM jumps up to 0.95V.

Thanks,

Russ

Hi, Russ

What I tried on AFE7225EVM to see correct VCM, I measured VCM after powering up without any clock input and it was 0.95V. And then, I set bit[5] of register 0x20A as '1' for single-ended clock input configuration. After this, the measured VCM was also 0.95V. Would you be able to duplicate this in your system first?

Thanks,

KW

Hi KW,

I don't see the same behavior as you do. I just tested it again, exactly as you describe above, and I measure VCM = 0V if I power up the board with no clock applied. I am measuring VCM on R88 (not installed) of the EVM. Once I apply a clock signal of at least 0.9Vpp (measured single-ended) then the VCM jumps up to 0.95V. If I remove the clock signal after that the VCM stays up at 0.95V.

Russ

You are correct. From my side, it shows the same as you. Something made me confused when I did.

VCM was 0V when powering up without clock. After configuring AFE7725 device and providing external clock, VCM was 0.95V. After removing clock, it stays around 0.75V. You can measure it from TP1 on EVM. Would you be able to duplicate this test on your proto system?

Thanks,

KW

Yes, I see the same behavior and same voltage levels when I measure on TP1. So it looks like the AFE7225 does not detect the clock input if the level is too low and then does not enable the VCM. Does that make sense?

Russ

Yes, I think so. I'll be trying to get more detailed clock input specs from designer of this device and getting back to you. will this work?

Thanks,

KW

Yes, it would be good to know whether this is normal behavior (and the datasheet's comment about LVDS levels is incorrect) or if we need to change some register setting to get it to work properly with LVDS levels. We would really like it to work with LVDS levels because we already built our hardware prototypes with the LVDS clock buffer and right now I don't have a good solution for the problem without changing the clock buffer and building new prototypes. I am working on finding a solution that I can implement on our current prototypes so if you or the chip designer has any ideas please let me know.

Russ

Hi, Russ

After power up, reset the device, apply input clock (as low as 0.2Vpp between CLKP/CLKM), then measure VCM. Note that resetting the device after power is first step to do.

Device supports a very low input clock voltage. See the performance (RX) vs differential input clock amplitude curve: Figure 6-13 from datasheet

If device was not working for low input clock amplitude, the performance would have been very bad.

Thanks,

KW

Hi KW,

I just tested this on the EVM and I do not see the same thing as you describe. I powered up the EVM, then pressed the reset button (SW1), then I applied the clock signal with an amplitude of about 0.3Vpp and the VCM was 0V. I had to increase the clock to about 0.9Vpp before the VCM went up.

I also tried resetting it with the EVM GUI software and saw the same result.

In our own firmware we were turning on the clock first before resetting and programming the AFE7222 registers but I just changed this to the other order and it does not fix the problem.

I see the plots in the datasheet now that you point them out, but it does not seem to work that way, even on our EVM. Were you able to test this on your EVM?

Thanks,

Russ

Hi, Russ

I duplicated your step on AFE7225EVM today.

1. Power up AFE7225EVM

2. Hit SW2 reset button

3. Configuring CDCE72010

After this, I was able to read 0.95V of VCM. Without step 3, AFE7225 device does not get any clock input. From AFE7225EVM design, the default clock input to CDCE72010 is J10 (CDC AUXIN). You changed it to J18 (CLKIN). so, you should read 0.95V of VCM step #1/2.

You are injecting 0.3Vpp which is around 0.1Vrms. This value is similar to -7dBm of external signal generator. Considering cable loss, you might have to give it 0.5dB of headroom.. it is around -6.5dBm. Have you tried this?

I'll modify our EVM tomorrow and duplicate your step.

Thanks,
KW

Hi KW,

Previously I had tested the AFE7225EVM by configuring the CDCE72010 to supply the clock and this works fine. It works fine because the amplitude of the clock is much larger coming from the CDCE72010. It is configured for CMOS single-ended output which then goes through the transformer (T9) to drive the AFE7225 differentially. This results in a clock amplitude of 1.25Vpp measured single-ended.

I have modified my EVM to supply the clock from J18 so I can use a signal generator and vary the clock amplitude. Here are my steps again in more detail:

1. Power up the AFE7225EVM with the clock signal turned off.

2. Press SW1 reset button to reset the AFE7225

3. Turn on the clock signal output from signal generator with the following settings: freq = 88MHz, amplitude = 0dBm.

4. Measured VCM test point as 0V.

5. Measured clock amplitude at CLKINN and CLKINP pins: about 400mV pp, measured single-ended.

5. Gradually increased clock amplitude while monitoring VCM until it jumps up to 0.9V. This happened at +6.9dB.

6. Measured clock amplitude at CLKINN and CLKINP pins: about 900mV pp, measured single-ended.

Please let me know what you find when you modify your board to use J18 as the clock input.

Do we need to configure the AFE7225 in some special way to use a low level differential clock signal?

Best regards,

Russ

Hi, Russ

I modified AFE7225EVM to use J18 as a sampling clock for AFE7225 and I duplicated your setup. Please refer to below steps.

1. Power up the AFE7225EVM with the clock signal turned off.

2. Press SW1 reset button to reset the AFE7225

3. Turn on the clock signal output from signal generator with the following settings: freq = 88MHz, amplitude = 0dBm.

4. Measured VCM test point as 0V.

5. Measured clock amplitude at CLKINN and CLKINP pins: about 550mV pp, measured single-ended.  (Each of signal generator can show level difference and different type of cable, cable length can also produce different level. Anyhow, I adjusted -3dBm of clock level to meet 400mVpp as you observed.)

6. Gradually increased clock amplitude while monitoring VCM until it jumps up to 0.95V. This happened at +4.0dBm from signal generator in my setup.

7. Measured clock amplitude at CLKINN and CLKINP pins: about 850mV pp, measured single-ended.

It look 3~4dBm (850mVpp) of clock input level required for AFE7225 to detect sampling clock. I'll check this with designer of this device whether we have correct value or not.

Thanks,

KW

Hi KW,

That's good we seem to have the same results now. But do you agree that this conflicts with what is stated in the datasheet for the clock input level range?

Russ

Yes, we got similar results. Please let me know page # or table # you are looking at from datasheet.

Thanks,

KW

Hi KW,

As I said in my very first post, the data sheet says on page 88:

"The clock inputs are versatile. The AFE7225/7222 can be driven by a differential clock, a single-ended
clock or two independent single-ended clocks. Low voltage CMOS for single-ended and LVDS for
differential are supported clock levels."

We are driving the AFE7225 clock input from the CDCLVD1213 clock buffer which has LVDS outputs.

Also, as you pointed out a few posts ago, there is a plot in the datasheet (fig. 6-13) which shows SNR performance vs. input clock level. It shows the SNR to be good all the way down to a 0.1Vpp differential clock input level.

Yet, we both have just measured on the EVM that about 0.9Vpp is required for the AFE7225 to detect the clock and start operating.

So something is amiss here.

Russ

Hi, Russ

I see. I'll get back to you after checking the setup environment for the measurement regarding Figure 6-13.

Thanks,

KW

Hi KW,

Have you found out any more about this problem?

I have in the meantime found a work-around that seems to solve our problem. The sample clock in our design is an agile clock generator so I start it at 1MHz and then after a 1 second delay I change the frequency to the desired 88MHz. The LVDS clock buffer has a slightly higher output level at the lower frequency and this seems to be sufficient to get the AFE7222 to detect the clock and start up properly. After changing to the higher frequency the AFE7222 continues to operate.

Even though this work-around seems to solve our problem right now, we have only done limited testing and I am still concerned that it may not work 100% of the time, on all boards, and in all conditions. The increase in amplitude at the lower clock frequency is quite small so the clock level may still be marginal for the AFE7222.

So I am still interested in hear what you can find out about this as there are still some questions outstanding. Is the information in the datasheet incorrect? Are the parts I have not working properly? Is there some register setting I need to correct to get it to work as stated in the datasheet?

Thanks,

Russ

Hi, Russ

I am talking about the difference of characterization setup and my bench setup with designer. He said 100mVpp (Single-ended) of amplitude worked fine with correct VCM (0.95V). We are trying to narrow down the difference of result. I'll be getting back to you with updates on Monday. 

Thanks,

KW

Hi, Russ

I duplicated this test today with 88MHz of CLK to J18 CLKIN on AFE7225EVM. I'll remove dBm scale info from external signal generator because output amplitude from signal generators would have some small difference and RF cable loss is also different. Please discard my previous result.

1. Power up the AFE7225EVM with the clock signal turned off.

2. Press SW1 reset button to reset the AFE7225

3. Turn on the clock signal output from signal generator with the following settings: freq = 88MHz, amplitude = 270mVpp measured single-ended.

4. Measured VCM test point as 0.95V.

5. Measured clock amplitude at CLKINN and CLKINP pins: about 270mV pp, measured single-ended.

AFE7225 works well even with 100mVpp (single-ended) as decreasing amplitude of CLK from 270mVpp in single-ended.

In your test, you got 0.95V of VCM at 900mVpp (Single-ended). There is gap more than 600mVpp between your test and my result.

Theoretically, 0dBm of amplitude from signal generator (Assuming no cable loss) will give you 316mVpp (Singl-ended) when you probe at R78/R82. Would you be able to try this first on your EVM?

Thanks,

KW

Hi KW,

I tested this again and I got the same result as before. Following your procedure above I measure VCM = 0V in step 4. The VCM only went up to 0.9V once I increased the signal generator amplitude higher. Once the VCM went up I measured the clock amplitude on CLKINN and CLKINP at 850mV pp single-ended.

Do you think there could be something wrong with the parts I have? The part on our EVM says on it:

PAFE722X

X238OH

TI 12J

P3C6 G4

And the parts on our prototypes say:

AFE7222I

TI 18J

P5CO G4

Is the part on your EVM different than these?

By the way, there is an error in your calculation of the theoretical peak to peak voltage for 0dBm power. The 316mV you state would be peak, not peak to peak. 

 Russ

Hi, Russ

I'll check your part number and discuss this with designer today. The part number on my EVM is the same as on your proto boards.

316mVpp is the value measured peak-to-peak setting by oscilloscope. Yes, peak-to-peak in differential has to be twice of 316mV. Anyhow, I'll update you soon.

Thanks,

KW

Hi, Russ

Would you be able to take off that device and ship it to us so that we can look at it? That looks proto version of device. I'll update you with shipping address if you can ship it.

Thanks,

KW

Hi KW,

I could remove it and ship it back to you but it will take some time and I am not sure that it would actually help us solve our problem. The ICs on our prototypes are different and I don't think they are proto versions yet we still see the same problem with them. Again, the markings on the chips on our prototypes are:

AFE7222I

TI 18J

P5CO G4

Best regards,

Russ

Hi, Russ

Do you mean you got the same issue (Required min of 900mVpp in single-ended for correct VCM) from "AFE7222I" device? This is not a proto device. The shipping address is for design team in India. If you are ok, you can send me this AFE7222I device to me and then I can mount that device on our EVM for the test. This looks better considering time saving.

Thanks,

KW

Yes, it appears to be the same problem, although I could not measure the required clock level in the same way as on the EVM because I don't have an input for an external signal generator. As I explained in my very first post, I am feeding the clock to the AFE7222 from a CDCLVD1213 LVDS clock buffer. The AFE7222 VCM does not come up reliably after power-up because the clock level seems to be too low. I had to remove the 100 ohm LVDS termination resistor to get it to work at all and even then it sometimes came up and sometimes did not.

I measured the clock level on our prototype board at 0.6V pp single-ended and the VCM does not come up reliably with that level. I had to remove the 100 ohm LVDS termination resistor to get the 0.6Vpp as the VCM never comes up with only 0.3V pp (standard LVDS level) when the termination resistor is in place. What I am doing now is starting our clock at 1MHz initially and then changing the frequency to 88MHz after a short delay. At 1MHz the clock buffer puts out 0.83Vpp single-ended and that seems to be enough for the VCM to reliably come up every time.

Since the AFE7222 datasheet says the clock input accepts LVDS levels, I would think that driving it from the CDCLVD1213 with the proper 100 ohm termination would work reliably, but it does not.

So even if the IC on our EVM is a proto part and may not be up to spec, we are also seeing the same problem with the real parts on our prototype boards.

Russ