Dac8581 interface with LM4F232

Hello Prateek,

I snooped through some of your old posts on the E2E Community, I see that you're participating in the TI India Analog Design Contest. Awesome! There seem to be a whole lot of entries this year, the results should be exciting. I'll try to address your questions below, but there are a few gaps and misconceptions in your questions.

PRATEEK ARORA1 said:

1. The board Lm4F232 does not have a dedicated pin for getting the System Clock. The DAC needs the clock for its functioning. Moreover I will be transmitting 16 bit data in a serial fashion (as DAC has serial input). How do I do this. I intend to send the bits 1 at a time onto a GPIO pin thats connected to DACs serial input.

First, let me address the misunderstanding of the SCLK pin that you have referred to as the 'System Clock'. This pin is not really a system clock, instead it is the clock for the serial interface (Serial-Interface CLocK). Edges of this clock will be used to clock in the serial word from your LM4F232 to the DAC. When you're getting acquainted with a new DAC or ADC it's handy to first look at the pin configuration section of the datasheet and the block diagrams. This will give you a good understanding on a high level of what the device does and what pins you have access to for controlling the device. 

Your proposal to use GPIOs as the serial interface isn't wrong. It is, however, highly inefficient and will slow down your code severely. I haven't used the LM4F232 evaluation kit before, but it looks like it makes almost all of the device's pins available at the breakouts along the sides of the board. The device features 3 SSI (Synchronous Serial Interface) ports that you can use to accommodate the signals the DAC8581 is expecting for SCLK, CS, and SDIN. The best part is that the module will do all the work for you! All you have to do is tell it what word you want it to put on the bus. You can read further about the peripheral in the device datasheet and in the Stellaris Peripheral Driver Library Users Guide if you plan to use the StellarisWare APIs.

PRATEEK ARORA1 said:

2. I believe the delay should be 45us between data bits at input. Is this correct (22.22kHz)?

I'm not sure where you got this number. With each SCLK while CS is low the device will clock in bits from SDIN. So the gating factor for 'how quickly bits can be shifted in' is simply the maximum SCLK period, specified in the timing requirements section of the DAC8581 datasheet. This figure is 20ns or 50MHz. The delay from one frame to the next is also 20ns.

I made a presentation concerning interfacing TI ADCs with Stellaris MCUs a while back. The same ideas apply to TI DACs. You can download that presentation here. I also have posted various sample code along the same lines here.

I hope this helps!