Trying to make use of the ADC124S021 quad ADC for fast reads of stepped DC signals (switching between pots with static DC values between 0-5V).
FIrst of all I find the timing and interface information very confusing in the data sheet. What I don't understand is why it takes a whopping 32 clk cycles for a single reading! This is ridiculous unless I am totally misunderstanding the protocol. It seems that you need to use 16 clk cycles to clock in the address of the channel you want to read and then you need 16 clk cycles to read in the data. 128 clk cycles to read 4 channels?
Why can't I simply read 8 bytes in a row (without addressing them)? This would require a mode where it assumes I start on ch0 and read all four in series.
From what I understand you send 1 byte with the address and then while the second byte (LSB) is being received it starts the conversion and then you need to read in two bytes which represent the result.
Does this sound right?
Secondly I have found that when I change an input voltage from say 1V to 4V (i.e. a large step) I need to wait about 2ms before reading the data otherwise it is completely wrong. My voltage source is buffered so it is a low impedence source and I have no filter networks in place that may slew the signal. I have no idea why it would take this long for the acquisition. Any clues?