ADS1675REF based board does not respond

Mariano -

Based on your settings, take a look at Figure 4 of the d/s and the timing requirements in the table underneath the figure.  From your description, it looks like you are potentially violating the master clock and SCLK limits (minimums).

Thanks for your answer Greg,

I need to to understand also how clock signal must be and its relationship with ext SCLK. Actually i can reach with my equipment a CLK frequencies not higher than 12 Mhz , delivering a CLK@12Mhz and setting SCLK_SEL to 1 and DRATE2:0 to 000  implies that i must apply a SCLK with a fixed frequency? or i can apply a SCLK from 0Hz to a X Higher value? If i must apply a fixed SCLK frequency how i can calculate it on different CLK frequencies?

SCLK must be delivered only after a DRDY pulse is detected? or i can apply it constantly as i have to do with CLK?

Another question

in d/s CLK signal must have HIGH LEVEL not less than 3.5V: is it normal that applying a 5Vpp clock signal to SN74 OR GATE  i see only 2.5Vpp half signal at its output applied directly  to ADS1675 ? How should be the levels of clock signal needed in input at or gate?

Thanks

Hi,

please let me ask another question always about this problem, which type of clock the CY22393 PLL of XEM3010 board provide to SN74 OR GATE? i mean in terms of voltage range and frequency?

Thanks.

I look forward to your reply.

MR

Hello,

please is there anyone that can give me support on this issues? i'tried to call phone support directly in italy but they told me that they cannot give me any, and the only place where i can put questions is here, E2E. 

Is the website experiencing problems? 

The clock provided to the EVM for the ADS1675REF is 3.3V 32MHz.

Hello Greg,

i've analyzed signals the best i can on the board and at the moment i'm focusing on clock signal delivered to ADC, 

i've asked a question regarding this on the apposite section of E2E community: http://e2e.ti.com/support/logic/f/151/p/243602/855261.aspx

and seems that the problem can be the OR gate, Chris Cockrill is telling me that i have to use SN74AHCT1G32 instead of SN74AHC1G32DRLR please can you check this? the 

BOM of ADS1675REF contains SN74AHC1G32DRLR ...is that the error?

Thanks.

MR

Hello,

i've applied a robust clock to OR gate and now i'm sure that 5Vpp digital clock is applied to ADS1675 pin 55..

but, in this configuration (CMOS interface with internal SCLK generation):

pin30:LVDS             1
pin29:SCLK_SEL    0
pin28:PDWN           1
pin32:LL_CONFIG   0
pin33:FPATH           0
pin34:DRATE2        0
pin35:DRATE1        0
pin36:DRATE0        0
pin38:/CS 0
pin37:START           1 (HOLD HIGH)

pin43:/DOUT floating
pin45:/DRDY floating

i have no signals on SCLK or /SCLK pins.. 

also i've noticed that also forcing to zero DR0:2 though my single board rio IOs results in having on DR2 a 0.8V signal and so not zero...

Is there a way to check if the ADC ADS1675 is faulty? the only "output" from it i can see is when i attach power supply with no clock on pin 55 is the OTRA led turning ON...

But when i apply the clock it turns off and since then simply i have no response at all from ADC ...

In the end i want to ask if there is a way to obtain support for this task from Texas Instruments ITALY, i'm wondering if there is an italian customer care for this.

Thank you

Hi there,

finally i can see data coming out from ADS1675!

i'm trying to build a very simple VI in LABVIEW on single board RIO FPGA to retrieve DATA OUT bits when DRDY goes HIGH but until now i still haven't found a working solution.

From timing characteristics when CMOS output and LOW SPEED 000 is selected i cannot figure out if every single bit of DATA OUT is available on every rising edge of SCLK...

on page 8 of ADS1675 data sheet seems that DOUT and SCLK internal are not synchronous... 

Have you some VI  specifically developed for communication with NI FPGA - ADS1675?

Thanks in advance!

MR