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DAC8411 / Vout updating speed. should we consider last 6 bits for updating speed?

Ryuji
Guru 20090 points
Other Parts Discussed in Thread: DAC8411
Hello,
 
I would like to know, output speed of DAC8411.
 
<Question>
-Please let me know wheter  DAC8411 can below opearation ?
 
1.DB23~DB6(18bit)  Serial data updating. (only 18bit updating)
2.After updating DB23~DB6(18bit),  Vout is updating.
3.After Vout is updating, updating again new DB23~DB6(18bit) soon.
 
-Should we consider last 6 bit(DB5~DB0) for the Vout updating speed ?
 
 
<These question's background>
In the datasheet P.28, last six bit of  DB5~DB0 are don't care.
So, Our customer  think that we can ignore last six bit and don't  input  last six bit.
Thus, customer think that  Vout updating speed is 18clock for 18bit only .
 
But, shift register has 24bits wide, so I would like to check for checking the updating speed.
 
Best Regards,
Ryuji Asaka
 
 
 
  • 0
    TI__Mastermind 46290 points

    Ryuji,

    This is explained on page 28 of the datasheet. On the 18th falling edge the command on the bus is latched in and executed. At that point sync can be brought high.

  • 0 in reply to Kevin Duke
    Guru 20090 points

    Kevin san,

    Thank you for the reply.
    As your information , can DAC8411 operate below operating ?
     
    I can't understand, when DAC8411 accept interrupt by sync pin.
    As page 28 of the datasheet, I think that  sync pin is load at the 18th falling edge only.
    But, we would like to send DB23~DB6 by 18CLK for shortening the updating time by skip the DB5~DB0.
     
    --------
    1. DB23~DB6 are updated by first 18th falling edge
    2. Sync is brought high soon ( t7=0ns ) after 18th falling edge.
    3.Skip the last 6 bits (DB5~DB0).
    4.After minimum sync on time( t8 = 50ns or 20ns) , next DB23 is wrote to register.
    5.next DB23~DB6 are updated by second 18th falling edge.
     
    repeat above 1~5.
    Please see the attached file as my operating image.
     
    Best Regards,
    Ryuji Asaka
     
  • 0 in reply to Ryuji
    TI__Mastermind 46290 points

    Ryuji,

    If SYNC is brought high any time before the 18th falling edge it acts as an interrupt to the transaction. If SYNC is brought high any time after the 18th falling edge the transaction is complete. As long as SYNC is held high for the minimum required time between frames this operation is fine. Your PDF looks fine. Your sequence looks fine.

  • 0 in reply to Kevin Duke
    Guru 20090 points
    Kevin san,
     
    Thank you very much for the reply.
    Let me ask to confirm to the operation.
     
    1.
    I would like to update as short as possible.
    So, we would like to use 18CLK cycles and 18bits only by SYNC is brought high after 18th falling edge soon.
    I will use SYNC pin as Reset pin after DB6.
     
    As your information, I can use DAC8411 as above.
    Is my understanding correct ?
    Please see the attached file P.2.   I exercus about clock cycles.
     
    2.
    I concerned that  DAC8411 need 24 clk cycle and DB5~DB0 for DAC updating due to below reason.
     a) In the data sheet P.7 there is parameter of "t9  24th SCLK falling edge to SYNC falling edge".
         So if we would like to update to DAC, there is minimum 100ns from 24th falling edge.
         Why is this parameter  t9  defined ?
     
     b) In the data sheet P.28 Figure 105., SYNC is brought high after 18th falling edge.
          But, there is DB5~DB0.
          If SYNC goes low after Min high time, Will be new DB23 visibled in behalf of DB5 ??
     
     
    Best Regards,
    Ryuji Asaka

    Best Regards,
  • 0 in reply to Ryuji
    TI__Mastermind 46290 points

    Ryuji,

    I understand your confusion. I took a moment to look at the digital block for the device and it's clear that the instruction is latched and executed on the 18th clock edge. Once SYNC goes high the state-machine for the serial interface is completely reset. Hope this clarifies that.

    The T9 figure should be observed from the 18th falling edge to the next SYNC falling edge. The device will operate as you expect.

  • 0 in reply to Kevin Duke
    Guru 20090 points

    Kevin san,

    Thank you for your reply.
    I understood that I can reset register by SYNC and updating again.
    I would like to calculate updating time.
    Could you please kindly let me know below?
     
    --------------------------------
    <1> Claculation of DAC updating time.
     At the condition of AVdd=5V 
     (a)  {1st updating:18clock cycle(20ns x 18)} + t9(100ns) +  {2nd updationg:18 clk cycle(20ns x 18)}  =820ns

     (b) {1st updating:18clock cycle(20ns x 18)} + t8(20ns) + {2nd updationgC:18 clk cycle(20ns x 18)} =740ns

     (c) If (a) and (b) are not correct, please kindly let me know correct calculation.
     
    *In my attached pdf file in the preview posted, I calculated SYNC high time as MIN high time t8.
     But, t9 is observed from 18th falling edge, my calculation is incorrect.
     So, please kindly let me know. 
     
     <2>
    As you said, t9 sholuld be observed from 18th falling edge.
    Will be revised this description in the data sheet?
    --------------------------------

    Best Regards,
    Ryuji Asaka
  • 0 in reply to Ryuji
    Guru 20090 points
    Kevin san,
     
    Sorry for the bothering you.
    Could you please kindly let me know about calculation of updating time ?
    <2> is not important now. I understood that , it is difficultly.
     
     At the condition of AVdd=5V 
     (a)  {1st updating:18clock cycle(20ns x 18)} + t9(100ns) +  {2nd updationg:18 clk cycle(20ns x 18)}  =820ns

     (b) {1st updating:18clock cycle(20ns x 18)} + t8(20ns) + {2nd updationgC:18 clk cycle(20ns x 18)} =740ns

     (c) If (a) and (b) are not correct, please kindly let me know correct calculation.

    Best Regards,
    Ryuji Asaka
  • 0 in reply to Ryuji
    TI__Mastermind 46290 points

    Ryuji,

    Case A is correct.

  • 0 in reply to Kevin Duke
    Guru 20090 points
    Kevin san,
     
    Thank you!
     
    Best Regards,
    Ryuji Asaka