Dear TI,
note: edited to change datarate to 11 full speed, was a typo at 00.
I have been studying the ads1259 and ads1258 per suggestions from your specialists here (thanks). I am using the ADC to measure step changes that will occur synchronously, just prior to the START pin assertion. Each START pin assertion is desired to provide only one fully settled conversion of the input, with one data readout. My system is an analog integrator that is measuring pulsed energy. Each pulse produces a unique response, and each ADC value needs to represent that response and only that response. The next and subsequent pulses require the same unique synchronous sampling.
I would like to do this as fast as possible (50 to 200 usec) with the best 24 bit performance. I would appreciate your review of the following definitions and timing I have learned from your datasheet.
1.) Initial delay - after START pin in low for a long time, when the START pin goes high, the first data read is delayed by some 800 f_clks in datarate 11. After this initial delay and the start pin has remained high or is brought high before the required setup time prior to DRDY , the second data read is at the datarate, and continues at the datarate as long as the start pin has remained high, or is brought high before the required setup time.
2.) If start pin goes high only long enough for one conversion to occur, will this initial delay be present for each start "pulse"? This would make the effective datarate equal to the initial delay rather than the datarate, when using the start pin to control single conversions.
3.) Initial delay from Standby and datamode:
The datasheet (fig 46) states/implies that FIXED mode has valid data on the 5th data cycle, when synchronous to the START pin. From this, I interpreted the total time for valid settled data to be the initial delay (51usec 802 f_clks) + 4 DRDY cycles (32 usec) = 83 usec for a valid read of the input from the START assertion.
The AUTOSCAN mode with one channel in list requires an initial delay of 45 usec before valid data is ready.
AUTOSCAN chosen to avoid reading bad data for 4 DRDY cycles to get fully settled conversion. I plan on reading only good data.
4.) Conversion Cycle timing:
Initial conditions:
Power on for 10 seconds or more
Registers setup for AUTOSCAN with only one channel in list.
11 Datarate
Internal f_clk with external 32768 Hz Osc.
000 Switch time delay
Analog inputs at 150 mv (zero signal)
START pin LOW
Conversion cycle:
:
Analog Input steps from 150mv to "Some value between 200mv and 5V"
1 Microsecond settling time for Analog input driver
START pin is asserted HIGH for 20-50 microseconds
START pin is driven LOW
DRDY goes active (LOW) 45 microseconds after START was asserted HIGH
Data is clocked out with DIRECT method 32/SCLK
Analog input steps from "Some value between 200mv and 5V", back to 150mv
:
Then between 200 microseconds and 10 seconds the system will remain idle (Standby) until conversion cycle above repeats.
The total time for this operation would be:
1 usec settling + 45 usec initial delay + 32 SCLKs
- with an SCLK of 4Mhz (32*250nsec) = 8usec + 46usec = Total conversion cycle time of 54 usec
Repetition rate of 18,518 Hz (without accounting for analog signal response characteristics i.e. step and reset times)
I plan on using the ads1258 for single channel, single cycle conversions at a repetition rate less than 10,000 conversion cycles per second.
Please let me know if my interpretations are correct, and any advice you have.
-- Andrew Duran
