My circuit is a copy of the reference design of the DAC161P997 evaluation board with a few things removed/changed to save cost.
I'm using the simplex configuration with an isolation transformer. That all seems to be working just fine. DIN and DBACK are transitioning as documented in the data sheet SWIF frame protocol. I'm sending frames in continuous mode D:0:(15 bits):P1:P0:D.....
ERRB is solid low indicating some sort of error condition.
SWIF interface is using a 525 Hz bit rate so the 1/4 bit transitions are occurring every 476 uS. Data sheet states minimum rate is 300 Hz so this meets spec. I have verified the signal timing and transitions using a scope to make sure the timing is rock solid and does not move out of the required timing ranges. I had to do a little software algorithm changing to get the 1/4 bit transitions at a very tight regular period. That is all very solid now. Also verified the start up sequence and that looks good. Starts up with a D symbol and then starts a frame with another D symbol. So 2 D symbols are sent about 100mS after power on.
Low voltage power supply is 3.3V and loop current power supply is 24V.
Example bit pattern being sent to device via SWIF
4000 uA (0x2AAA)
D:0:0:0:1:0:1:0:1:0:1:0:1:0:1:0:1:0:1:0:1:0:D
P1 = 1 (3 bits are 1 in TAG and MSB)
P0 = 0 (4 bits are 1 in LSB)
I can send schematics via e-mail if you need them. Cannot post here for obvious reasons.
I can get scope trace of DIN DBACK if you need them.
